Super-FinSim is Fintronic's top
performance, fully compliant Verilog
simulator. It supports PLI 1.0, SDF, VCD
and provides through integration with
third party source level debuggers,
waveform displays etc. a complete
simulation environment on all popular
platforms. FinSim provides the flexibility
of mixed compiled and interpreted
simulation and an efficient incremental
compilation.

Fintronic has a mission to supply the
highest performance Verilog HDL
simulators available for full language
design verification and timing simulation.
It is privately held and privately funded

Download File Size:281.05 MB

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