x32
Cadence Design Systems, Inc., the leader in global electronic design innovation, has released 15.20 version of SSV Platform Products. From synthesis through implementation through signoff, Cadence’s full-flow digital design platform provides a fast path to design closure and better predictability.
Where traditional tools fall short, our platform has been developed to help you meet power, performance, and area (PPA) targets and deliver your products on time.
Cadence Voltus IC Power Integrity Solution is a full-chip, cell-level power signoff tool that provides accurate, fast, and high-capacity analysis and optimization technologies. The Voltus tool is of particular value to designers for debugging, verifying, and fixing IC chip power consumption, IR drop, and electromigration (EM) constraints and violations. Use the tool to:
- Calculate and analyze power consumption
- Analyze and optimize EM and IR-drop (EMIR)
- Analyze impact of power on design closure, from chip to package to PCB
The Voltus solution includes innovative technologies such as massively parallel execution, that can be either multi-threaded or distributed-processing, and physically aware power grid analysis and optimization. Beneficial as a standalone power signoff tool, Voltus IC Power Integrity Solution delivers even more significant productivity gains when used in a highly integrated flow with other key Cadence products, including Cadence Innovus Implementation System, providing the industry’s fastest design closure technology. When used with Cadence Voltus-Fi Custom Power Integrity Solution, a transistor-level electromigration and IR-drop (EMIR) tool delivering foundry-certified SPICE-level accuracy, the resulting platform accelerates IC power signoff and overall design closure.
More info: https://www.cadence.com/content/cadence-www/global/en_US/home/tools/digital-design-and-signoff/silicon-signoff/voltus-ic-power-integrity-solution.html
Cadence Tempus Timing Signoff Solution is a complete standalone tool that delivers silicon-accurate timing signoff and signal integrity analysis that ensures operational chips after tapeout. By tightly coupling the design implementation environment with the timing signoff environment, the Tempus solution enhances timing convergence throughout the design flow and greatly reduces the time to design closure.
As well as being a stand alone tool, Tempus Timing Signoff Solution integrates with both Cadence Innovus Implimentation System and the Virtuoso Platform.
More info: https://www.cadence.com/content/cadence-www/global/en_US/home/tools/digital-design-and-signoff/silicon-signoff/tempus-timing-signoff-solution.html
About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2007 revenues of approximately $1.6 billion, and has approximately 5,100 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.
Name: Cadence SSV
Version: 15.20.000
Supported Architectures: x86
Website Home Page : http://www.cadence.com/
Interface: english
System Requirements: Linux
Supported Operating Systems: RHEL 5, RHEL 6, SLES 11.0
Download File Size:2.39 GB
|
