URL : http://www.altera.com/products/software/products/quartus2/qts-index.html


Quartus II software enables the highest levels of productivity and the
fastest path to design completion for both high-density and low-cost FPGA design.

Dramatically improve your productivity compared to traditional FPGA design flows.
Take advantage of the following productivity enhancing features today:

TimeQuest timing analyzer is a new, next-generation ASIC-strength timing analyzer
supporting the industry-standard Synopsys Design Constraints (SDC)-based timing
analysis methodology.

PowerPlay power analysis and optimization technology provides automated power
optimization capabilities and helps you effectively manage power from design concept
through implementation.

Incremental compilation supports the bottom-up design flow that allows design blocks
to be created and optimized independently. System architects can incrementally integrate
optimized design blocks while the performance of the design blocks is preserved
throughout the integration process.

SOPC Builder eliminates mundane and error-prone system integration tasks and allows you
to build systems in minutes.

Push-button physical synthesis technology and the automated Design Space Explorer (DSE)
simplify design optimization.

Extensive cross-probing support between tools helps identify and correct design issues.

The pin planner feature (PDF) enables easy I/O pin assignment planning, assignment, and
validation.

Complete command-line and tool command language (Tcl) scripting interfaces give you
advanced scripting capabilities.

Download File Size:737.59 MB

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