ALINT is a highly optimized Verilog design rule checker. It includes a
complete set of STARC Design Style Guide rules to use in your next ASIC
design. STARC is a consortium of 11 Japanese ASIC foundries that has
established a set of design rule guidelines for corporations to follow
based on a set of best-design practices.

Top Features:
Verilog Code checks, design elaboration and synthesis emulation
Clock Domain Crossing (CDC)
User Modified Design Rules
Fast analysis of complex ASIC/FPGA-SOC designs
Cross-probing of Error messages to source code
Configuration Manager
Supports STARC Design Rules

Download File Size:96.61 MB

---