Want a powerful, yet easy to use simulation environment?
SynaptiCAD's simulation and debugging tools provide a
standard interface for controlling all of your simulation
tools. SynaptiCAD's timing diagram editors have the most
extensive and accurate timing analysis features available in
any timing diagram editor on the market including delay
correlation, reconvergent fan-out, and clocks that model
jitter and buffer delays. Three different levels of editing
let you pick the best price and feature set for your
application.

Free yourself from the time-consuming process of manually
writing Verilog, VHDL, and SystemC test benches. Generate
them graphically from timing diagrams. SynaptiCAD provides 3
levels of test bench generation to meet all your design
needs. SynaptiCAD offers support for the latest test
equipment and emulation technologies allowing you to port
your simulation and timing analysis data to your prototyping
environment.

http://www.synapticad.com/

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