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Synopsys, Inc., a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, has released Service Pack 01 for Synplify L-2016.03. This software delivers faster runtimes, better performance, and accelerated development of high reliability and functional safety applications
Synopsys’ FPGA design solution is a comprehensive suite of tools that together provide FPGA designers with the necessary features to deliver any FPGA-based design to market faster and with the lowest design risk. The combined tool suite of Synplify Pro and Synplify Premier synthesis and Identify® RTL Debugger provide designers accelerated time to first hardware with deep debug visibility, fast integration of fixes and optimal performance for FPGA-based products.
Synplify also supports specific market requirements like high reliability techniques that allow for operational reliability in high radiation environments such as satellites, human safety areas such as factory floors and data centers requiring the ability to run, reliably, 24/7, and DSP design with Synphony Model Compiler.
Synplify Pro FPGA synthesis software is the industry standard for producing high-performance and cost-effective FPGA designs. Synplify software supports the latest VHDL and Verilog language constructs including SystemVerilog and VHDL-2008. The software also supports FPGA architectures from a variety of FPGA vendors, including Altera, Achronix, Lattice, Microsemi and Xilinx, all from a single RTL and constraint source. Synplify Pro software uses a single, easy-to-use interface and has the ability to perform incremental synthesis and intuitive HDL code analysis.
For designers of large designs that need the fastest possible synthesis runtimes and the highest quality timing, area and power results. Synplify Premier software provides all of the features of Synplify Pro as well as a comprehensive suite of tools for advanced FPGA design.
Synplify Pro logic synthesis includes:
- Incremental, block-based and bottom-up flows for consistent results from one run to the next
- Automatic compile points incremental flow for up to 4x faster runtime while maintaining QoR
- Accelerated runtimes with support for up to 4 processors
- Scripting and Tcl/Find support for flow automation and customizable synthesis, debug and reporting
- Optimal area and timing results using FPGAs from Achronix, Altera, Lattice, Microsemi, Xilinx
- Hierarchical team design flow allowing parallel and/or geographically distributed design development
- Comprehensive language support including Verilog, VHDL, SystemVerilog, VHDL-2008 and mixed-language design
- FSM Compiler and FSM Explorer for automatic extraction and optimization of finite state machines from RTL
- Graphical state machine viewer to automatically create bubble diagrams for debugging and documenting FSMs
- Automatic memory and DSP inference provides automatic implementation of a design with optimal area, power and timing quality of results
- Incremental static timing for analysis allows updates to timing exception constraints with immediate visibility into results, without re-synthesis
- HDL Analyst interactive graphical analysis and debug tool for design diagnosis, problem isolation and functional and performance analysis
About Synopsys
Synopsys, Inc. accelerates innovation in the global electronics market. As a leader in electronic design automation (EDA) and semiconductor IP, Synopsys delivers software, IP and services to help engineers address their design, verification, system and manufacturing challenges. Since 1986, engineers around the world have been using Synopsys technology to design and create billions of chips and systems.
Product: Synopsys Synplify
Version: L-2016.03-SP1
Supported Architectures: 32bit / 64bit
Language: english
Supported Operating Systems: Windows 7even / 8.x | RHEL 5-7 (Red Hat Enterprise Linux) / SLES 11 or 12 (SUSE Linux Enterprise Server)
http://www.synopsys.com/
Download File Size:1.57 GB
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