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Cadence Design Systems, Inc., the leader in global electronic design innovation, has released an updated (ISR2) IC 06.17.700 Virtuoso. The Virtuoso suite of tools facilitates the full-custom design of integrated circuits. The suite offers a wide range of design and verification tools that provide complete front-to-back solutions for varying design requirements, such as full-custom integrated circuits and digital integrated circuits.
CCRs Fixed in IC 06.17.700 ISR2:
The IC6.1.7 ISR2 stream is a cumulative stream of all hotfixes that are submitted after the base release.
1546330 Update Lib List: cellviews marked for deletion
1544092 Functions with EvalType Sweep get wrongly evaluated in Assembler with attached testcase
1541777 Statistical corner gives different result compared to it's corresponding Monte Carlo run
1536919 ICADV12.2 FCS gives warning: An unexpected error occurred while applying uifPushGlobalCDFState SKILL function
1536633 Item name of Include form is different from Verifier
1535637 wspdata_to_tcl does not seem to be converting all the data
1535060 Detail Route crash with standalone CSR
1533061 systemVerilog netlister generates wrong netlist when all bits of a bus are not part of I/O port; verilog netlist is fine
1532787 Autorouting with WSPs using netGroups for constraints (probably allowedWidthRange) crashes
1532136 Getting the uifPopGlobalCDFState stacktrace
1531648 zpcellSCRATCH views are created during copy command in IC6.1.7
1530366 Different simulation results when comparing sequence and value-based statistical corners
1529990 Ocean XL fails to run reliability analysis in ICADV12.2
1529966 Using VAR for stop time netlists incorrectly if initial condition is also used
1529906 VerilogInteg breaks spectre iterated instance netlisting
1529285 Stream out with Virtual Memory button checked fails
1529120 Pin To Pin Crashes
1528798 Make _pteGetMPTSupportMode() a public function
1528651 Navigator displays top level cellname after descending in an instance
1528056 Cells edited in ICADV12.2 FCS cannot be opened for edit in ICADV12.1 ISR 15
1527350 UNL netlist is missing parameters
1526741 Flatten instance is changing pin label names
1526702 Schematic Check has no warning markers for one of the "floating nets"
1526269 Collision of stipple pattern between cdsSymbolicDevice and customer PDK
1525282 vfibatch still does not support license queuing
1525157 Create bus is dropping wire segments in some circumstances
1525083 Why do Multiple Patterning options exist in IC6.1.7
1524801 ADE XL hangs when trying to create a troubleshoot point in a Netlist-reference Monte Carlo simulation
1524395 Cells edited in ICADV12.2 FCS cannot be opened for edit in ICADV12.2-64b.404.2
1524335 FGR evaluated fail with IC6.1.7 when fluidGuardRingInstallPath points to IC6.1.5 ISR6
1523923 auCDL does not honor hnlMaxNetNameLength when name exceeds 255 characters
1522884 UNL fails when irun in wrapper
1522817 long run time for extraction when backtracing is enabled
1522538 create wire does not correctly use the active layer when different shape types overlap
1522065 When pin_style option of extract_net_connectivity is changed from labeledShapes to ConnectedShapes, changed option is no
1521386 inherited connections are not correctly propagated with use of force descend
1520892 ADE L crash when using Netlist-and-Run
1520834 SKILL Lint reports INTERNAL ERROR (BADRULE) on namespace
1520036 Marker in ViVA XL did not display correctly
1519930 Crash when some opens are displayed in the Annotation Browser involving weakly-connected instance pins
1519621 leHiLayerTap crashes when clicking on syEnh contacts
1519333 equivalent nets are also part of isolation condition
1519231 crash in ResultsViewEventFilter::eventFilter when using ADE XL
1518978 assign_term and unassign_term expect different busbit characters
1518925 use absolute current value in Partial Network Optimization
1518910 Partial Network Optimization does not see DC Op Current
1518835 create bus incorrectly offsets wires by grid point depending on location of instance pins
1518549 EAD - LIL/Poly contact not created on the fly as in PVS
1518288 M1 strap routing is detoured when M2 trunk exists
1518259 IC6.1.7 FCS Modgen Topology Router routed same conditions with different topologies
1518254 IC6.1.7 FCS Modgen Topology Router failed to route collision twigs
1518166 constraint manager driven WSP routing flow issues
1517808 Netlisting does not work if two place masters refers to single switch masters
1517390 Create measurement broken when it comes to highlighting centerLine of paths/pathSegs as snap targets
1517250 Virtuoso should print a warning and refuse to load incompatible plug-ins
1517049 SMG-61005 error occurs if freetext is used with bus pin
1516330 power_down_function does not includes analog supply for a digital pin
1515815 simulation takes long time to start
1515755 With auCdlCDFPinCntrl set, auCdl netlists duplicate connections in subckt instantiations, mismatched with subckt defn
1515743 Setting "dpt" "displayMaskColor" to nil gates leSetLayerVisible from working in ICADV12.2 FCS
1515638 level shifter with power and ground voltage shifting to be defined separately for each voltage shifting during export
1515492 command for ground voltage range for Level Shifter is extracted even when there is no voltage shifting
1515025 Markers to be generated when twigs do not fully land over trunk or pin when using twig routing
1515005 Markers to be generated when vias are not maximized using TwigRouting
1514957 MPT Update Color fails to detect coloring changes
1514738 Selected Label display is not recognizable when zoom out in IC6.1.7
1514553 reliability analysis setup form GUI elements resize incorrectly
1514547 Advanced options tab in reliability analysis missing fields in ICADV12.2 FCS
1514383 Bucket Sizing not obeyed on performing particular series of steps
1514367 High precision extraction in EAD reports shorts where fast extraction and Layout XL do not see shorts
1514352 geCreateHilightGroup crashes Virtuoso
1514153 Crash issue appears when seeing the selected stdvias through Property Editor in EIP mode
1514026 Update issue in canvas when changing cell through property edit
1513941 Special character in Description needs to be transferred based on XML syntax rule
1513678 Resolve four color MPT error message
1513408 Blockage attribute "effectiveWidth" not updated correctly in "Property Editor Assistant"
1512869 Slider should move back to original point when using ctrl + Shift + another key
1512840 HTML Status Report is wrong
1512560 DEFin result does not follow wrongway min width for M5 and M7, M4 and M6 work fine
1512539 crash during routing
1512363 'Attempt to Use Double Cut Via' impacted by setting wide edit default CG
1511723 Cannot stretch a simple pathSeg
1511711 fim_out parameter omitted from ac/pac analysis when simulated from OCEAN
1511573 ViVA XL "Swap Sweep Var" shows data from wrong history run
1511342 ocean histogram function generate error
1511162 Twigs need to be matched on per segment basis
1511083 create label middle mouse drag incorrectly positions labels
1511019 Noise units are incorrect via plot all waveforms
1510789 Performance issue of moving implementation up/down in Verifier GUI
1510780 Cannot place double cut via by Create Wire
1510687 Finish Bus fails when only 2 bus bits are selected; succeeds if all bus bits selected
1510486 ADE L parametric set sweep with Spectre looks for OASIS license
1510211 During extraction, LDO cell is extracted as stdcell instead of macro model
1510176 Pin check variables cause netlisting error if cell has no pin
1509841 Hierarchy Manipulation: Wants to control pin layer for Make Cell command
1509776 envSetVal issue for rowGroundWidth and rowPowerWidth in ICADV12.2 FCS
1509742 Tie shielding (using RiDE tcl) of pre-routed wires are not correctly connected
1509292 DEFIN drops connectivity in ICADV12.2 FCS
1508972 Crash with dump stack(virtuoso:dbPanic+568()) after croute
1508951 Vias from create bus do not follow minSpacing constraint
1508862 Dumped techLib fails to list required trackPattern constraints
1508845 SMG Building Block "replaceXZ" will not work when the output is connected to an internal net
1508681 Jmax_life not working as expected in ict file using Voltus-Fi
1508256 ViVA XL crashes while refreshing waveforms
1507571 symbol and symbol_xform - hnlHandleMultiplePlaceMaster = "ignore"
1506689 Why is the browse button grayed out on the Edit-Object-Properties form
1506620 Display of sub-window is incorrect if scale is set
1505814 Shape that has over 200 vertices does not convert correctly by XOASIS Out
1504065 Create wire fails with WSP snapDef if a trackPattern constraint is present
1503992 AMSD netlist error with global bus
1503909 Pass/Fail no longer first column in output in detail transpose view
1503655 Finish trunk on the same layer left a gap to target trunk
1503307 CDLOut does not remove all iPars when it appears multiple times in a parameter expression
1502846 DRD PostEdit/Verify Design resets the power domain enable variable for VDR to nil
1502600 ADE XL mismatch and other analyses broken due to change in model setup with latest foundry models
1502470 sublevel color locked vias are allowed to be incorrectly color locked at the top level, resulting in color conflicts
1502269 Xstreamout generates different result even if using same template file
1501682 Hier Manipulation: Make Cell breaks clone structure
1501558 incorrect color map of thermal region
1501469 Generate Selected from Source delay when instantiating 10,000 transistors
1501353 DEFout fails with a stack trace when using ICADV12.2
1501195 Incorrect range output from awvSaveToCSV SKILL function
1500959 Path vertices changing in XStreamOut
1500797 VSR with "Maximum Pin Width" and "Use Pin Width to First Via" options does not work correctly
1499367 constraint view is corrupted, causes (CMGR-1808): Constraint member of type net is out-of-context because OA Exception
1499088 Virtuoso crashed when plotting schematic to PS file hierarchically
1498880 Abstract loses locked state on colored pins if nets are not extracted
1498522 Hard to select vertex when zoom in very close with pixel-based gravity
1498103 Clones(Synchronous Copy) are not retaining color
1497518 Abut All' in Modgen cannot abut the transistors properly as when chaining
1497472 ADE XL Results->Detail-Transpose display misalignment
1497295 num cuts were optimized by "Widen To Fix EM Violations" but it made short errors
1496920 EAD options: wrong ADE XL results when nets under test are selected through Parasitic and electric setup
1496854 readPath and writePath attributes omitted from ~>?? DPL output of ddLibType, ddCellType and ddViewType objects
1496710 need an option 'Select only in Canvas' in the Edit Properties form
1496704 Browse button on Edit Properties form should be re-enabled when form initialized
1496030 Extractor is extracting rather long switch function
1495891 Tcl script returns error "empty input name or member is not valid"
1495885 update net connectivity creates guides to actFill shapes
1495815 dbInstSetLayerShifts fails with poor message on 4 color layers
1495649 support the custom cell handling in CLP which are registered as stdcell for extraction
1495586 analog port in macro model are mapped to non-analog ports at top design model
1495482 stdcells registered using cpfSetStdLibCells API are extracted as macro
1495281 ADE L cannot evaluate hspiceD termMapping expression in 6.1.6 ISR13
1494634 Add hierarchical checker violation categorization to differentiate samecolor versus diffcolor lock violations
1493816 Output expressions using the sample function are not plotting from ADE XL in ICADV12.1 ISR13-15
1493756 Row/Col of CAV0M1 and CBV0M1 standard vias controlling issue for local intercontact layers
1492976 Cannot pick the wires from VIA by Create Bus with multi layer function
1492971 Public function getCallingFunction wrongly flagged by Lint ?checkPvtFuncs as Cadence Private.
1492516 If the order of connecting pins is not the same from source to destination, the Finish Bus command creates short result
1492422 The Create Label command with auto mode creates a label at wrong position
1490898 AMS results not available at the end of a run using snapshot feature
1490247 Tooltips missing in Software Product License Management form
1489847 CPF-1594 coming for port connected to instances in same domain
1486513 Modgen routing leaves opens - QOR
1486383 Incremental binder requires too much info to bind 2nd instance
1486095 Incomplete Nets error occurs if a single via object is used for two metal objects connection
1485956 unsurround dummy does not remove backannotated dummies
1485507 Copy expressions or signals from one test to another very slow when there are many lines
1485133 Crash in Real Time Tuning
1484503 ADE XL view is not invoking gdmdelete to delete managed files
1484382 Synchronous clones not updated when colors change on one clone
1484123 Taper to Pin Width style downsize tracks when same layer
1483156 enclosure calculated by AutoVia is incorrect
1483104 Track Pattern Assistant is not refreshed when WSP file is loaded
1483035 Opening Maestro view does not set current window
1482991 sublevel colored pin shapes are not extracted correctly
1482294 Shape not placed at spacing shown by DRD (enforce mode)
1481702 postCreateObj trigger not working when compression enabled and DMTYPE is set to none in Library Manager
1481556 OASIS_Simulation_Interface license error when using Spectre parametric simulation second time from ADE
1481506 shutoff condition consist of signals from different power domains
1481480 Issue with ground voltage shifting in Level shifter
1479763 Align command should remember last entered layer
1479749 Routing in VSR on WSP's with preroutes causing unroutes and DRC errors
1479009 OSS netlister fails on global bus syntax
1479003 UNL netlister fails with global bus net syntax
1478991 Cannot save ADE state - original state is overwritten with empty file
1478919 VSE copy hangs
1478882 Wire Editor does not enable 45 degree end connection
1478336 GUI: change Pint2PinR to Pin2PinR
1478259 Crash experienced when tapping a layer
1477813 Use Open Advanced BBT Library checkbox becomes unchecked after setting
1477803 Use Open Advanced BBT Library By Default in SMG
1477710 To extend M2 to make it longer to satisfy MinArea rule during P2T
1476898 libNameSel of spectre.mdlOpts errors out when set through .cdsenv/.cdsinit
1472253 Fixed via cannot put during automatic routing in VCAR
1472027 In the EAD resimulation flow, netlist has warnings and does not simulate
1471701 Stretch of Fluid Guardring with the pr boundary cause a crash
1470490 "Next" button not working when same cell is opened more than once in Tools -> Find/Replace GUI
1467865 Power IR/EM needs to handle the new format for length and width units in the EXT15.11 QRC extview.tmp
1467858 delete pin caused crash
1465646 The all/none buttons in Applications to Cross Probe form overlaps with another View Type button.
1464867 cannot launch EAD with layout in read mode
1464268 Voltus Fi GUI results metal/via display issues for 55nm process
1463935 vpaOptimizePins SKILL function to include all the GUI options as arguments
1463076 Load .grf plots from incorrect result set when Specify new results database is used
1459185 Changing the plot flag in the ADE XL Outputs Setup is extremely slow with large number of expressions and signals
1458066 Four segments bus QoR depends on its coordinates
1457889 Cannot plot waveforms after Monte Carlo simulation with .measure
1457427 In IC6.1.6_ISR12, cannot generate netlist for postlayout simulation due to hnlHandleMultiplePlaceMaster default value changes
1456663 Dimming option "dimmingAutoEnabled" not set correctly when setting through envSetVal or leSetEnv
1455960 To add right mouse click in propEditor tree for functions of deselect, select only and zoom into
1454583 minVoltage not to affect maxVoltage and vice versa
1454539 techSetLPPriorityInContext should keep the techProps of an LPP propagated to the parent technology database
1454391 weAutoDropViaForOverlaps does not insert vias between a wire and an instance pin
1454335 Virtuoso_Layout_Suite_XL license is checked out in read-only mode with VLS L
1454264 Support Lock Color options in the Create Bus command
1453852 VSR testcase to improve QOR when routing gets hard to close
1453764 PathLength(drawn),width(drawn) and need W(drawing) incorrect value
1451541 verilogOut repeats bus for iterated inst
1451093 To debug causes for un-connects on a smaller testcase based on std cells
1450483 Eye Diagram Assistant - infinite loop when freq equals to 1/2G
1449572 systemVerilog netlister generates wrong syntax netlist for replicated bus names
1449378 Want ability to deselect objects in canvas from Edit Properties form
1448998 Relaxed spacing was used and middle pathSegs were not compacted
1447614 QoR issue with single connection on pin db var
1445729 "Swap sweep var" shows results from previous plots
1444242 defin gets minWidth wrong from techfile
1441674 strand route fails to route a multi-port net with and without region based tracks
1441150 PGV generation with vfibatch has large number of taps not associated with nets
1438368 mapi ordering issue when VHDL instantiates Verilog
1436923 Query L shape spine in Partial Select can't apply to all pathSegs.
1433134 Automatic dimming setting up issue when we do it through an env var
1433077 Netlist generation failed for "LNA_BB" cell from "rfLib"
1426022 subckt definition not getting netlisted in ADE MTS
1425951 *Error* _amsExpandPath with "spectre.envOpts" "dspfFile"
1425678 Update Lib List in Virtuoso should not prevent saving ADE cellview state to valid library
1424419 EAD assigning incorrect EM limits to adjacent vias in via clusters
1422631 Crash in Virtuoso after leHiCreatePath
1421401 EAD assigning incorrect EM limits to adjacent vias in via clusters
1412920 Make the library property form non blocking so that the Library Manager is responsive while the form is displayed
1407781 creating multiple constraints is very slow
1407776 Deleting lot of constraints is very slow
1406291 Plotting VN2 from ADE XL actually plots VN
1405409 delay function gives incorrect result for family waveform
1404700 AC Operating Point Backannotation does not work
1403797 Increase parallelization of simulations for WCC in Automatic mode
1402734 Improve results load time
1402620 dimmingAutoEnable Layout env variable is not working
1396669 fix_length is unable to match lengths despite having plenty of space
1368885 Alignment of the options on the Reliability Analysis setup from is disturbed when the form is resized
1359828 layerSet manager as a separate window causing focus stealing.
1344847 DPT: Update color or recolor makes Virtuoso unresponsive
1337805 Edit locks not released after the cellview being edited is closed
1335288 flattenPcells option causes stream-out to fail when read only detailed_rc.oa file exists
1332779 The dimmingAutoEnable env var for Virtuoso Layout does not change auto dimming
1331540 dbCopyFig creates extra rails while copying dbRows
1307026 Missing simulation status in runams using IC6.1.6
1299553 Cell opened in edit mode but cannot be saved
1276013 Create label creating some labels at wrong locations when using middle mouse button feature to label multiple shapes.
1272639 VN2() waveform with wrong unit for ADE XL run
1264178 DRD inconsistent in flagging net class constraint violations
1252054 XStream does not convert half width pathSegs to polygons during stream out
1238935 Incorrect net is probed when probing a net with multiple inherited connections at different levels
1151572 Update Constraints shifts MODGEN 828510 do not require combining each technology under single block
About Cadence Virtuoso System Design Platform. The Cadence Virtuoso System Design Platform is a holistic, system-based solution that provides the functionality to drive simulation and LVS-clean layout of ICs and packages from a single schematic. There are two key flows: implementation and analysis.
The implementation flow is used to create an IC package schematic in Virtuoso Schematic Editor and then transfer the schematic data to Cadence SiP Layout to layout the physical design. In addition, this flow offers the capability to generate and verify library parts, output a bill of materials (BOM), and perform layout versus schematic (LVS) checking.
The analysis flow is used to extract and simulate any portion of the system (IC-package-PCB) regardless of the layout design status. Moreover, this flow offers the capability to automatically generate schematics for the PCB and IC package layouts, bind the instances of the IC package to the ICschematic or models, and build testbenches to simulate the system using the Virtuoso ADE ProductSuite plus Spectre Multi-Mode Simulation interface. Cadence Sigrity models extracted from the PCB and IC package layouts get automatically stitched into the generated schematic.
More info https://icerbox.com/WgYKJXpn/virtuoso-system-design-platform-ds.pdf
Standalone Software Shipped with IC 06.17.700:
- Virtuoso Power System L (IC6.1.7)
- Voltus-Fi Custom Power Integrity Solution XL IC6.1.7
- Dracula Design Rule Checker (4.9)
- Dracula Layout Vs. Schematic Verifier (4.9)
- Dracula Parasitic Extractor(4.9)
- Dracula Physical Verification Suite(4.9)
- Dracula Physical Verification and Extraction Suite (4.9)
- Virtuoso Chip Assembly Router (11.3)
About Cadence. Cadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry.
Product: Cadence IC Virtuoso
Version: 06.17.700 ISR2
Supported Architectures: x86
Language: english
System Requirements: Linux
Supported Operating Systems: RHEL 5, RHEL 6, SLES 11.0
http://www.cadence.com/
Download File Size:4.01 GB
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