TestBencher Pro generates reactive VHDL, Verilog, OpenVera, e, and
TestBuilder test benches and bus-functional models from language-independent
timing diagrams. The generated test benches are capable of applying
different stimulus vectors depending on simulation response so that the test
bench functions as a behavioral model of the environment in which the system
being tested will operate. TestBencher Pro is an excellent tool for testing
large FPGA and ASIC designs.

More at..

http://www.syncad.com/

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