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Systems, Inc. , the leader in global electronic design innovation, has unveiled XCELIUM 19.09.001 is part of the Cadence Verification Suite and supports the company’s Intelligent System Design strategy, enabling pervasive intelligence and faster design closure.
fixed in XCELIUM 19.09.001 1524869 CORE_AMSD irun always compile elaborate even though nothing changes
svams fails with multiple global supply error
update the xmvlog: *F,NOECBF error message to aid in MS binding debug
Request for a tool command switch to locate the AMSD directory - bigger picture: need ability to control compiled IP
duplicate port specification at Verilog/SV and SPICE boundary causes SFE-46 error - request better error message
Cannot bind Verilog module to Spice when using bus ports
SVRNM: Support SIE models with mixed-language net connections
Support Electrical signals as control signals in CPF
Xcelium AMS: xmsim: *E,SYFATAL : `$clog2' - Unsupported system task/function.
SV nets with custom resolution function don't find SVAMS CMs when connected to electrical modules
Need rnm_coerce on switch that is complementary to rnm_coerce off
RNM Debug: Question about creating a breakpoint on a wreal signal/port using TCL stop command
RNM Debug: Question about creating a strobe on a wreal signal using TCL strobe command
$SIE_input is used on a port with EEnet, all the real pins in the block. On the top level but the values is not computed
Provide a switch to downgrade PIEMRSG error to warning
Scoped ie card with nettype causes E,CUVNCM (No connection module found) error
Valid spice OOMR's are ignored with autospiceoomr option
Unexpected UDFUOBJ and CSNIHT when using a rmn custom vct in 3-steps
CUVMCP: Recursive multiple concatenation for digital block
xmvlog -zparse dumps different file content for 32bit and 64bit
INTERR: sv_seghandler - trapno -1 addr(0xc5) in cu_xvlog_cmp_signature
LPS(UPF) - 18.09-s005 improper exit - control signals is resolved as electrical by DR optimization
Allow hierarchical reference in create_power_nets and create_ground_nets commands in CPF
more intelligent discipline resolution default logic assignment for designs that do not require disres
Degradation in Xcelium vs Incisive – related to RL_bidir.vams update in Xcelium
MSIE+SVRNM: Internal error during elaboration with RNM coercion
xrun in multi step compile need to find AMSCOMM automatically
W, AMSNLOG is not expected for a design with no MS content
Invoke SimVision standalone also checking out Xcelium_SC_DMS_Option along with "Affirma_sim_analysis_env
Call of schematic in Standalone invocation of simvision checkouts Xcelium_SC_DMS_option feature
XMELAB improper tool exit with message update_power_domain - invalid power domain
Spurious AMSNLG warning with "xcelium.d.rtl", used with -xmlibdirname.
MSDEBUG: Parameters which are expressions should be displayed in evaluated form
VerilogAMS analogmodel instances currently not processed for schematic/symbol rendering
Remove current probes from instance parameter string in schematic tracer
MSDEBUG: Remove requirement of -snapshot option when invoking Simvision with MSDEBUG flow
MSDEBUG: add r3 model type to analog primitive/symbol binding flow
How to remove '2 Virtuoso_Multi_mode_Simulation' from license options
outstanding error *E,WUDNSP in xcelium
AMSD : Inverter instance is not inverting the input
Customer experiencing internal error in xmelab
Invalid BNDERC with reused design
Improve the CCSNAN error message on real variable
xrun (xmelab) Internal Exception error in mixed-signal design
BNDERC error when accessing SV UDN struct through virtual interface
AMS fails when DPI-C is used with Spice On top
DMS CPF testcase unresponsive at elaboration stage; stuck at amspwrParsePrimaryPGNets()
add an option to disable PIEMRSG error during elaboration on selected nets
Getting 'xmsim: *E,SYFATAL : $clog2' - Unsupported system task/function' in an AMS-SV run
Remove sqrt DPI import from EE_pkg.sv file
Using genvar in a generate block with OOMR gives wrong results
XMELAB: ams_add_to_td_list - parent data already in child internal exception error
Elaborator tries to insert isolation cell for nets already having level shifter and isolation as a part of functionality
Elaboration trapno -1 : xmelab internal error during mixed signal IP Reuse(via VIPER) flow for top-level MS verification
Need xrun option to print soft error and allow pure SV elaboration for real port connected to logic variable
Internal exception xmelab message ams_mk_disciplinep - no discipline
FATAL error for mixed language testcase using $SEI_input function
Using ams_weak_setd argument with xrun the elaboration fails with internal error
AMS - Boundary port domains are not honored for macro CPF level in AMS
Analog signal being used as isolation control gives CCSNAN error
Downgrade errors PIEMASG and PIEMRSG to warnings
Elaboration internal error related to mixed signal on boundary with VHDL 3 party VIP
Virtuoso Verilogams Import: Symbol default parameter values are not properly
Internal exception error in AMS Low Power simulation with stack trace in ams_pwr_get_active_ordinary_id and ams_pwr_get
disabled_count being incremented by 1000
elaboration performance - NY HDC xTb
Behavior of assertion change between 18.12 to 19.10 xcelium version
ABVCTR warning does not have enough debug info
xrun elab Internal Exception error when using $assertoff in code
Builtin system function <> not yet implemented
Simulation deadlock in 19.03 whereas it finishes in 18.03 stream.
Internal Exception Error during compile/elab of design
Provide detailed information on COD generation for UVM/SV code
Need to show srandom calls in dbg_seed tracing
ncvlog_cg internal error 'gq_gen - SVHR type mismatch'
Internal exception on 18.09-002, Incisive works OK
NCSIM Internal exception with message "Continuous Assignment: (File: XX)"
xmvlog_cg *F, SOPARM causes a elaboration failure
xmvlog_cg internal error gq_mvlabel - no blocks
Urgent issue: ncsim MESSAGE: T(0): sv_seghandler - trapno -1 addr(0x15b)
Internal error at xmvlog-cg stage "gq_pop_constraint - wrong identifier"
xmelab: *E,CUVCGF: Code generation for worklib.uvm_pkg:sv <0x41231003> failed.
elaboration internal error due to uvm_ml_adapter_imp with 19.03
Xcelium causes infinity loop.
xmvlog_cg, *F,INTERR: INTERNAL EXCEPTION gq_finalize_stuck_at_behavior
Provide detailed information on COD generation for UVM/SV code
xmvlog_cg internal exception error with - gq_e_concatenation - word not a tab
PERF : C function svh_castcheck is required to be inlined for standard classes.
Toggle coverage for mod ports inside interface needed
Change expression table for control scoring to take into account short circuiting
support for toggle coverage for modports needed
Toggle coverage support for I/F and modport ports for a module needed
Request interface/modport ports toggle coverage for a module
Unsupported bins-with syntax
coverage pragma not turning off expression coverage when vector scoring is enabled
CNDIR expanded message does not include all reasons why directory cannot be created
Request Toggle Coverage Support for MDA of enums
CNDIR expanded error does not tell user about exceeding linux character limit for directory name
Add support for toggle coverage in instantiated SV interfaces (modports).
Request interface/modport ports toggle coverage for a module
Adding ignore bin to covergroup causes simulation slowdown 10x
CGBNOL warning even though there is no overlapping bins
Internal exception when using set_refinement_resilience and -v200x
Smarter analysis of statically unhittable expression terms in control coverage
Need support toggle coverage for I/F modport
Need option to do pure type-based code coverage to reduce memory footprint
expression coverage not scored properly when $unsigned system function used in expression
SOP expression with nested ternary doesn't seem to be correct
I want to turn on block coverage, but not per-instance block coverage. I only want type coverage. I don't see any way
Add support for toggle coverage of interface modports
vManager improper exit - Can't open coverage analysis.
Internal exception when excluding signals w/ -ere
FSM arc is not scored but it must be according to the code
Coverage merging consumes excessive amount of memory, causing improper tool exit
merge of parameterized vector signal shows incorrect range in Variables Pane
expression is marked uncovered when function call used in one term of the expression
xmsim INTERR when -conditional left out of set_expr_coverable_operators
Incorrect number of bins detected in a cross cover point
vManager client crush on coverage merge
Coverpoint sampling issue on element of an array of packed struct
xmsim INTERR when enabling enum array toggle coverage
(Update) FSM Coverage Analysis in IMC show some transitions as uncovered even when the waveform shows the transition
xrun of previously existing snapshot with coverage enabled causes INTERR
bad coverage when function used in expression coverage with set_glitch_strobe
Getting issue in dumping code coverage data base. Using TOOL: xmsim(64) 18.03-s009
INTERNAL ERROR on coverage dumping phase
IMC FSM transition coverage not being scored correctly
smart_refine: Smart exclusion wrongly excludes extra struct signal
expression is marked uncovered when function call used in one term of the expression and vector scoring is enabled
Internal exception during xmvlog_cg
Coverage model generation iterates over unnecessary instances
code coverage causes INTERR
INTERR xmvlog_cg: Unexpected signal #11, program terminated (null)
Incorrectly reported overlap bins warning CGBNOL
Solve…before on array size results in EXPITT error
solve…before on array size results in EXPITT error
Please enhance the solve before with hierarchical_identifier
Solve…before on array size results in EXPITT error
ncelab: *E,CUINFI
SOPARM error/extended error need improvement
celab: *E,INNOTR :: initializing Virtual interface using interface instance created inside vhdl_entity
*E,INNOTR when SV i/f bind into VHDL + uvm_config_db::set
OOPR to interface enhancement request
Support OOPR for interfaces
SV interface binding issue
ncelab internal error when trying to blackbox/bbconect a module thats getting binded
ncelab: *E,INNOTR :: initializing Virtual interface using interface instance created inside vhdl_entity
Please enhance CUVPOM error to report module/instance name that has the bad port connection
SVBMUF error message should provide hints to use instance binding
xmvlog: *E,EXPITT (): Expecting a variable of an integral type
Support assignment to interface member from one primary to another
SVBDUPI error when instance is already bound when using -libmap or -compcnfg with -nncbind
TYCMPAT error does not have enough information to debug
Enhance CUVUNF error to print out instance path of the module which caused the error
misleading error message regarding non-constant operand assigned to parameter using $sformatf.
Enhance CUVUNF error to include instance name of problematic block with the OOMR
EXPITT with solve x before y.size
CUVUNF elab error on single irun MSIE when adding unrelated bind statement to the CU
Elaboration not giving required warnings when using sv configs
NOTDOT for member select of interface port
VCFGUUR not generated without -libverbose
VCFGUUR warning message when running with SV configuration and MSIE single irun
xmvlog: *E,EXPITT: Expecting a variable of an integral type.
verilog config or libmap file not working as expected, need better ERROR message
Enhancement req. xmelab: *E,DSSUFE (MSIE) Unsupported formal expression in port connection
Regarding xmelab NOTDOT error
xmelab: *W,EVBPRM: bad parameter value in (-gpg) association (pp => /abc/e).
xmelab: *E,NOTDOT when using $bits on svi signal
configverbose - add first level module where liblist is applied to
xrun internal exception
Confusing error message TYCMPAT for misspelled symbol
Xcelium config liblist does not warn about non-existent library
Unable to understand the warning from MSIE v2k config support warnings
VPI returns wrong lib name when queried for hierarchical vpiConfig property
OOMR to a VHDL object specified in SV force is not supported .
CUIMBC error with interfaces
Support for unpacked structure as a datatype for mailbox
cross language boundaries for binding of modules issues CUOOMR
VHDL bind with SV interface does not work
Calling $size on VHDL to check array size not supported
Elab failing (internal exception) with xcelium 18.03-s009 version: MESSAGE: if_alloc - <= 0 bytes
xmelab: *E,MULAXX
xmelab: *E,ICDPAV
Need ability to turn on -warnmax 0 for specific mnemonics
xmelab: *E,CUCIHD : Class inheritance hierarchy instantiation depth (100) exceeded.
Internal error on final incremental snapshot build with multiple primtop
localparam bug in Xcelium version 2018.07.001_agile
xmelab: *F,SOPARM (<..filename..>): Special otp not parameter (529).
struct used for mailbox not supported
(MSIE) :Report error for inconsistency for vhdlsync option with incremental partition
CUPARF on parameter evaluation for a virtual class
elaboration becomes slower at "CHECKPOIN 15 (after cu_doic1)"
config uses incorrect libraries for binding
elaboration performance
Improper tool exit during elaboration when MSIE is enabled. addr(0xc058)
erroneous CUIOAI error message generated when referencing hierarchical reference inside generate block
RTL test case Internal Exception during build with Xcelium EHF versions 19.01-a001-20190110 & 19.02.a001.20190117
xmelab: *E,CUVUNF error in single step MSIE for out of module reference inside uvm class from module
Improper tool exit during Elaboration on 18.09-s06 (also tested with agile release18.12-a01) used in 64 bit mode
Internal error - xmelab/LP - via_get_corresponding_interface_highconn_object
Elab takes 3 hours for digital case with generate and array
Internal exception error with Auto MSIE
(Dynamic Test) *E,DLNORD codegen error
internal elaboration error with signature: cu_xrenumber_tablet() - We depend upon a tablet which has NULL upscope
Incremental snapshot build taking long time in SDF testcase
MSIE, a tool failure for elaboration
Breakpoint issue
xmsim Internal Exception error: MESSAGE: svh_find_itable_entry : Entry for uvm_reg not found inside uvm_reg_map
xmelab: *F,SVBDUPI (./m1.sv,14
(Dynamic Test) xmsim Internal Exception error with $fseek
xmelab: *E,DSSUFE (./aa.v,1
internal elaboration error with test case that passes in GREEN
Unexpected CUVUNF on sum with expression without valid array type.
elab performance slow with varying delay in the tran
xmelab NOTDOT with $bits usage in Hierarchical name not allowed within a constant expression
xmelab DYNGPE hierarchical reference from one primary to another primary
SARC : Error SVBMIM on primary build
Huge performance overhead on incremental partition build due to class specialization unification
Code generation exception error on incremental build : gq_datatype_write_net - vbits/!TAB or CAB
Internal exception error when DPI-C is used in parameter declaration.
improper tool exit during elaboration
xrun internal error when putting multiple pacakges as ancillary tops in single primary makeprim
2 dimension array parameter value was overwritten incorectly in generate block
xmelab: *F,SVMLED: System virtual memory limit exceeded.
Elab won't finish, more than 24 hours
internal elab error related to interface in1803/1809/1903 consistently
-betaperf causes Int. Exception Message: cu_vifc_xtrack_semantically_single_caller_pass1 - fork-join/ no function-task
Wrong error: MULAXX Multiple drivers to always_comb
xmelab: *F,INTERR: INTERNAL EXCEPTION : MESSAGE: ddict_create - called whem ddict system is not ready
MSIE improper tool exit while running incremental: xmelab: *F,SVMLED: System virtual memory limit exceeded
xmsim crash with fseek function
Customer seeing E,CSGMSS on 19.03.002. Are there any options to avoid this error?
xmelab: *F,INTERR: INTERNAL EXCEPTION error observed with partition compile
xmelab, *F,INTERR: INTERNAL EXCPETION
Internal exception during elab when migrating from Incisive to Xcelium
Internal Exception during HAL linting with message sv_seghandler - trapno -1 addr((nil))
XCELIUM tool crashes during elaboration stage
MESSAGE: sv_seghandler - trapno -1 addr((nil))
MSIE fails on TYCMPAT however MONO works well
xrun: *F,INTERR: INTERNAL EXCEPTION in incremental build of parallel build
msie build suffers with internal exception sv_seghandler
xrun internal exception error when trying to recompile a design
parameterized classes show different default values when compared, casting fails for valid case
internal exception sv_seghandler found at elaboration
Wrong behavior with binds while trying to connect a port that doesnt exist in parent/destination module
TBBLDF error generated when xrun ran with -dpiheader and -errorchk 3
ivia_pair_sanity_check - vst and ot mismatch : Internal Exception
Internal error occurred during elaboration
VHDL internal error during elaboration, while accessing records
xmelab INTERR : cu_sigpv after adding (-lps_sv_interface_port_enh, -lps_viso)
xmelab: *F,INTERR: INTERNAL EXCEPTION cu_dvpm_get_fsigid_offset - unexpected nettmp_vhdl_driver
error in passing interface through modules instantiations in generate block
liblist based configuration reported via -configverbose
VHDL Elaboration internal error with vserror
Unexpected CUVUNF in hierarchical reference primary to incremental
multi-Tiered hierarchical gate level model Flop not properly propagating value unless probed
SDF annotations are different with Incisive and Xcelium
SDF annotation result different between IRUN and XRUN gate level simulation
INTERCONNECT multi source int delays does not annotate correctly.
How to set pulse control to specific instance/module
(GLS enhancement) Warning message is for ignored INTERCONNECT delay.
xmelab: *W,TRNDELAY: Moving the Interconnect delay on net :TB:uut_TOP.top_ana_inst.RESET_inst.IOFT outside of the tran n
GLS : Simulation result is incorrect, even if same SnapShot is used.
SDF annotation not matching in Incisive and Xcelium
gate simulation issue with improper SDF interpretation.
Internal Exception during elaboration when using SDFs with Negative delay and -negdelay
18.09-s006, Internal Exception error during elaboration using SDFs with Negative delay and -negdelay
"-entrandelay" option make iopath delay 0.01ns shorter
Xcelium with options "ENGATECDPMO -tch_stap_cnt 2 -enable_town" shows strange behavior
csi-xmelab - CSI: *F,INTERR: INTERNAL EXCEPTION with sv_sighandler - trapno -1 ((nil))
tranif0/1 delay behaves like Rise/Fall, instead of ON/OFF
GLS sim tool exception error
resetting and rerunning gatelevel simulations with dynamic SDF annotation results in SDFNET warnings
tfile could not work normally
Hold time timing violation with huge hold value, negative timing calculated by tool seems not correct
(MSIE) INTERR, MESSAGE: ptrblk: rwire is supply
Internal Error during running $dumpvars
Issue with backannotation - Signals become undefined when crossing the scope of the design
Internal error during simulation when SDF is annotated.
xmelab Internal Exception with sv_seghandler -trapno -1 addr message
Internal exception during gate level elaboration.
continuous assignment does not work for unpacked dimension signal
xmelab: *F,INTERR: INTERNAL EXCEPTION
xmelab: *W,SDFRDE: Read error for default code, skipping annotation of chip_top.verilog.sdf.worst.gz.X.
Difference in SDF annotation seen between Xcelium and Incisive
support VHDL attributes to define RTL parts as always_on
Support isolation in SV interfaces
SVI arrays are not supported in low power simulations (UPF)
support of create_power_state_group along with all new -supply/-group… options in add_power_state
Enhance IES to support the same supply net in both RTL and UPF
UPF: wildcards in connect_supply_net -ports don't work on UPF ports
LBRTPM message reports internal_power, direction internal, as mismatch with RTL
(lps-cpf) Handling of escape character in Verilog object
Print a NOTE when an SDA attribute is encountered that LP doesn't recognize
(NCsim): UPF restore_condition issue when 3-d array with multiple assignments
add support for add_power_state_group and add_power_state_group -group
Always block not getting replayed after power up because the driver is an OOMR
Support supply nets defined in both the RTL & UPF .
Tool is not connecting the power port of level-shifter isolation combination as per expectation
*E,NOPPIN:Primary power doesn't exist in Liberty cell
Support of clk_low retention model
Isolation outside of terminal boundary using -sink
*E,ILLAKO with multidimensional array pin driven by create_power_switch -ack_port
(UPF enhancement) support of create_power_state_group.
1801_LINT_CMD6 Tcl issue in command: extra characters after close-brace
Command support request: create_power_state_group & add_power_state -group
(UPF) set_repeater command support
(UPF) -applies_to_boundary support
support for -power_source in LP simulation
UPF : Not Insertion a virtual ISO on boundary of MacroModel
State retention performance enhancements
nxmbind with CPF causes ILLOBJM messages, old bind does not
ncelab Internal Exception error while migrating from INCISIVE to XCELIUM
the behavior of connect_logic_net without -reconnect is unexpected
*W,SNDRMU should list the drivers responsible for the warning
message identifying a missed connection when there is a rtl with liberty cell instantiated within another rtl with liber
Manage collision between HDL nets and 1801 supply_nets
make automatic connections to liberty cells that are instantiated within SV bind code
xmlib2cdb generates a strange error
ncelab: *F,INTERR: INTERNAL EXCEPTION ( sv_seghandler - trapno -1 addr(0x8) )
xmlib2cdb support environment variables in in -lib_mfile
Support implicit port connections in 1801
LP MSIE INTERR because of an internal msie file
Force is not reapplied after domain is powered in 18.09 with CPF
xmelab Internal Exception error: cuv_lpeswait - not ESWAIT
alias upf onto hdl for pg pins defined in same scope
Same lps options(5) exist in betaperf and new perf
Simulator Internal Exception error while running UPF sims
DFF doesn't recover if you use SV interface to pass clock and reset
Remove direction check from lps_pa_strict
Xcelium issues incorrect error when a define_power_model -for contains a list of cells
UPF produces internal error
Isolation added during synthesis, but not in LP simulation
Unprotected LPS assertion file which made by -lps_verify_unprotect causes Warning.
Forces in LP consume huge amount of memory
nmi DFF doesn't recover if you use SV interface to pass clock and reset
lps_relax_hierarchy option : the report of instances name displayed twice.
Integrate 1801 Linter bug fix release
dma_req_pending DFF doesn't recover if you use SV interface to pass clock and reset
Low Power simulation crash during wake up after a deep sleep
lps_iso_hybrid doesn't generate NORPCN error for missing explicit connections to backup power of ret cells
Generate error message if create_power_domain -exclude_elements is used
Provide time spent in liberty compilation as part of -status3
xmelab: *E,PSCNFLT: (LPS) A power source domain and its base domain cannot be declared as power source simultaneously.
1801 processing incorrectly issues error if object of create_logic_port/net already exists
Power up restore not working with clk_low_strict
Reset is not honored in the new clk_low_strict retention model
LIBDTM should Not be a soft error message
Phase 2 implementation of clk_low_strict retention model
add location of force command to *E,FONOVA error message
*E, FONOVA causing several tests to fail in pre-qual
Clock low strict retention latch gets corrupted on the save edge
Support latest UPF linter ( d016)
clk low strict retention applied to latch even though -target_type flop is in state retention rule
Spurious LP force at power-up causes test failure
Do not create NOISELE for design top without testbench when -location self is used
make xmelab: *W,CFLCPG a strong error instead of warning
Message on the ARM retention rule violation
*W,LPSFREXPR warning in LP simulation with latest green release
Registers getting excluded from retention policy for no evident reason
Make the option -lps_pacell_disable_ic default behavior
xmelab internal error in LP simulation
Replay of continuous assignment outside of process not executing on wake up
Internal error on apply_power_model with customer design
port in UNDETERMINED while using pre-compile liberty - in 19.06.e313
*E, PSILLPM: (LPS) A power source domain and its mapped parent domain cannot be declared as power source simultaneously
State retention of packed struct type register doesn't work correctly
Force disappears incorrectly in LP simulation resulting in test failure
set_design_attributes does not get applied when used at the top level
UPF : PST result is incorrect when to use logic_expr_drives_supply_expr attribute.
elab error with *W,LIB1801/*E,UDFUOBJ - UPF commands like create_power_domain are not applied when cell has liberty
INTERR when PA models are used instead of NPA models
Forces do not work for array of instances as expected
xmelab *F: INTERNAL EXCEPTION during elaboration with Xcelium 19.03s005
LP issue - always_latch doesn't wake up when power is turned on
Will the retention work if the simstate of retention supply is in CORRUPT_ON_ACTIVITY state?
SNDRMU warning - show net name rather than port name
Internal exception when simulating with UPF
Reset is not honored for a clk violation at restore_edge with clk_low_strict retention even if the reset is asserted
improper exit during elaboration at pwr_ptop() with EHF kit 19.08e419 which has clk_low_strict retention phase 2 fix
Internal Exception during elaboration in pwr_ptop () while running the design in 1909 Beta kit
protected typedef not allowed in incisive
covergroup instance is dumped even though instantiation/new is in code that is not hit.
ncvlog internal exception error due to undefined variable. MESSAGE: p4_mexpr - default VST_U_EXPRESSION
Internal error with ncvlog due to wrong selection of label's name - Unexpected signal #11, program terminated (null)
False parser NOTFXX error for struct initialiser
Ports being treated as variables when they should be wires
deposit prevents verilog actual driver
Add switch to prioritize packages in own library.
*E, UNDIDN: Undeclared identifier even after using typedef.
constraint reference to struct/union in class defined in package results in ILLHIN error - works in vcs
inline constraint does not recognize class object from a parameterized class of an inheritance
INCISIVE Compilation is 8X slower as compared to competition
typedef derived from 2-state typedef becomes 4-state
some parameters not being passed correctly when parameter functions used
E,ILLHIN unresolved when refer the member variable of base class in constraint block.
option to convert all compilation warnings to errors by single flag
Linking macro with string in readmemh
Inline constraint on object member variable not working when class being randomized is a mixin
The defparam doesn't overwrite to parameter.
A comment after the /* sparse*/ declaration results in error:E,REGSOV:(./rtl_memory.v,12
Incisive / Xcelium segfault on generated RTL
Incisive segfault on Stratus generated RTL
ncvlog internal error issue 'el_start_list_at - increase EL_NESTSIZE!'
xmvlog can't handle Japanese Character as syntax error
xmvlog internal exception with relax_svbind_target and new bind
xmelab internal error with relax_svbind_target: MESSAGE: cu_process_declaration - VST_E_UNKNOWN
input ports with unpacked array dimensions defaulting to variable instead of wire
macro cannot be parsed inside quotation marks
Unexplained ILLHIN: illegal location for a hierarchical name (in a package)
recompilation failing on SV import of vhdl packages with -v200x switch
INTERR - smi_set_sm - object is only a SMI_1ST class yet sel == 1
xmvlog internal error on February agile release
SPDUSD warning suppressed with -q even after promotion to error
Getting UNDIDN error when vectors are referred from extended class.
xmvlog Internal Exception error on nightly debug agile
WBINOPAR needs to be an error
xmelab *F via_get_ots_field: No ots structure of kind 49 exists
compaliation error at non-defined area
default_array_input_wire not working on unpacked array of ports with bind syntax
Unexpected NOPAR in assignment pattern with field name matching function name
constraint solver not consistent on array size
constrain on array element is ignored
Problem with SV constraint
Randomization problem with function-argument call
2D array with inside constraint on the size
Change of randomization order needed?
Unexpected failure from foreach loop referencing 2D array
Randomization performance issue in 14.21
Randomization is taking a very long time and increases runtime memory footprint 10times.
False contradiction when using sum() on object elements
Constraint contradiction for a solvable constraints
Randomization performance degrades as simulation progresses
Randomisation failure
Randomization distribution not correct in Xcelium
disable soft not working on element of array of object.
Functionality of soft disable on a class array element.
Multi-pass issue with pre-TRAT. TRAT is failing over: array size on inner dimension ( rnc_array.cpp,
xmsim: *E, RNDCNSTE due to "Solve before not allowed on empty array"
Problem constraining 2D queues
Need to make this Multipass testcase working with TRAT
xmsim: *E,RNDCNSTE (./const_struct.sv,13
TRAT_NOT_IMPLEMENTED: array size on inner dimension
TRAT not implemented instances in customer code
Array resize and multipass
Enhance SVRNC to support solve-before on MDA items
Randomization with soft constraints creates unexpected results
support limitation of calculation floating point number in constraint
Solver is giving a contradiction message, same partition solved on previous versions
randomization Internal Exception – Assertion !wif_lists_empty failed
Make XLGENENV have N severity instead of W and make XCELIGEN__* env vars work silently
*W,RNDOCS, conflicting constraints on dynamic array sizes. (Failed on TRAT, too)
Partition is giving a contradiction on 19.01.a001 but solved on 18.07.v001
Constraint solver multipass shows contradiction
Multipass needed to solve multi dimension dynamic array
W,RNDCNSTW output shows a randomize call in the pre_randomize() call of the actual problematic randomize call
Partition is showing a contradiction message with xceligen , solved properly on earlier release
real constraints partition contradicts on 19.01 solved on 18.07
Randomization not working properly
Xcelium 18.09 randomize performance even worse than IES 15.22.038
Incorrect RNDFUNAC warning, polluting log files
Getting SAT timeout for unclear reason
RNDERR cause Internal exception in TRAT
Internal exception in the solver. Pointing to: rnc_node_solver::rr_add_enum_ranges_to_wif(…
Randomization performance issue seen with user testcase
Solver solves with a value that does not match constraint
Incorrect randomisation results, caught with checkers=2
New solver order alg is causing an error with latest nightly
xmsim: *F,SCSIG: Signal SIGFPE raised by a SystemC library call from user application code.
TRAT is failing for customer with latest nightly build
MESSAGE: sv_fpehandler - user generated SIGFPE
TRAT failover possibly causing pre_randomize to not be called
Randomization failure without any explanation
Xcelium Constraint solver seems to ingnore the constraints.
TRAT solver fail with "rolling over to Pre-TRAT mode" then Internal Exception
Partition solved on 18.06, takes X60 more time on 19.03
RNDALF: Not enough information to debug
Constraint solver has problem interpreting a parameter if it is a 2-dimensional packed array.
segmentation fault in simulation
randomization doesn't work properly
TRAT solver required for a constraint but causes improper exit in 19.03.s005
Randomization error in 19.05. Was working in 19.04
RNDCNSTE for constant guard expression
SVRNDF error seen in TRAT
Constraint size failure of multidimensional array through foreach command for second dimension
segmentation fault from CCMPR02108424 reappearing in 19.06.a001
INTERR Internal Exception: illegal list underflow - stacktrace shows svrnc calls before exception
static_analysis_data::replace_var_arefs: rand aref on assoc array ( rnc_solver.cpp,5726 )
TRAT still failing to call pre_randomize
Simulation is failing with rnc error inside wpi.cpp
SV constraint solver doesn't honor soft constraint
Not possible to probe SV structs with BIG arrays
Subprogram body: PRINT_NODE (line: 775 in design unit UVVM_UTIL.HIERARCHY_LINKED_LIST_PKG:body)
VHDL2008 compilation: internal exception
Internal Exception with OSVVM
ncsim/RTSOVF - max size of dynamic array provided in error code message is incorrect
Systemverilog support for force of an entire unpacked array.
TSKFUN does not give enough information to debug problem
ncvlog: *E,UNSFRC (test.sv,8/27): Force/release of unpacked array nets is not currently supported.
process::halt not effective for children of finished threads
Memory RTL Model Performance Enhancement
Please update ncprofmem.pl in xcelium installation so it matches Xcelium Branding
x-prop fails to detect behavioral construct === 1'bx
$countdrivers memory consumption issue (3G)
The process-based save/restore creates a .process_save directory which doesn't follow umask settings
fine grained xprop enables
using 'xrun -write_metrics' modifies UVM_TESTNAME xrun plusarg
Complimentary scanning failing due to specman filter being automatically applied to incorrect logfile
xprop fox mode not propagating X for synchronous flop
Supported VHDL OOMR target (signal) is giving error when hierarchically referenced.
Internal Exception seen in Incisive
SAIF format not readable by Synthesis tool
Significant slowdown from non-blocking assignments
Compilation internal error with vst_class() - null ptr
xmsim *F XPROF Internal Exception error
INTERR: SIGSEGV in non-blocking assignment to virtual interface variable from class
memory profiler numbers are not consistent
internal simulation error sv_seghandler - trapno -1 addr((nil))
xprof Internal Exception error with MESSAGE: Xprof database dump failed!
xmsim Internal Exception with specify block and -sdf_simtime in MSIE flow
xmprofmerge.pl does not exist in the install area
-mem_xpof -profcstk not showing relevant information
index from for loop in fork/join mixed
Multi-step MSIE internal error during simulation, however Mono and 1-MSIE works fine
-memdetail loosing track of freed memory
-memdetail should provide memory footprint overhead on memory report
Simulation failing
replay wreal internal error with rpl_traverse-inspector
The log information is incorrect when to use -status and -simlogsize both.
customer testcase failure with "newperf" option
xmelab internal error: vst_contains - id not identifier, class 750
xmelab internal error: cu_update_assign_amalg - bad subsumed
Dramatic performance degradation when probing dynamic arrays
Xmelab internal error : vst_contains - id not identifier, class 750
xmelab error: flatten_expr - index selects of arrays not handled yet
fault simulation internal error with HDLICE memories
Entire regression results showing as failed in vManagerCS though some are passing
(FATAL) Failed to create timer thread (errno: 22)
Xprop issues XFAINC warning message but generate-endgenerate hierarchy path is valid
VHDL record port does not get value from packed struct
Dumpsaif does not generate a toggle count for implicit wire connection
Performance issue with L2W on parameterized modules
LTW - -enable_var_opt_core changes BNDWRN to BNDERR
xprop – x not propagating when delay is specified with time unit
CLONE internal error: sv_seghandler trapno -1 addr ((nil))
Functional discrepancies between 2 same simulation, works fine with linedebug and fails without linedebug
Collapsed network of converted logic has been forced: Provide messages to help in debug under option
assign statement fails to update under -enable_var_opt_core
Sometimes D=>Q cannot transfer in always block
internal Elab error with L2W - sv_seghandler - trapno -1 addr((nil))
internal Elab error with L2W dt_is_array hit unknown datatype
xp_elab.log corrupted
nettmp_is_finalized - id out of range - Internal Exception error during elaboration, introduced by -enable_var_opt_core
sv_bushandler - trapno -1 addr((nil)) - SIGBUS not in rts_xfer -enable_var_opt_core
INTERR: cuv_pewaitset - reads (but not writes) to non-wire during xprop testing
logic-real-logic connection behavior changes with LTW
SST2ER: SST2 interface error: Series sort buffer maximum size reached.
Switch naming and messages to use Var to Wire
Internal Exception error when dumping waves and coverage is enabled with en_vaca_opt(default setting)
improper tool exit during Elab with VTW file
flatten_expr crash during elaboration with VTW
How to improve FSDB dumping performance , which is about 1.1~1.6x time behind competitor.
Simulator internal error while trying to add a signal to the VCD database
Elab improper exit when W access is removed from build
Severe degradation in Elab time: "After third cu_dop2nlrefs"
Mirror on array of reals provides an internal exception error
mirror to array of reals issue unexpected Error : *E,NCTYMM
xmsim tool failure when dumping VCD for gate-level mixed-signal design
Xprop issues XFAIND message for a named for-loop block within generate/endgenerate
xmelab *F, MESSAGE: dt_get =_known_datatype hit unknown datatype
INTERR sv_seghandler
xmsim internal vst_root if_ptoroot
TCF file written by xcelium was adding non-numeric string (,) in the duration value
Customer design fails with -ENABLE_NTICM
TCF file for VHDL generate block is not complete
VL_XMBV suppresses xprop warnings
Need help debugging source of PROPTH error
Xcelium internal error with VCD dumping
FATAL ERROR DURING INCREMENTAL COMPILATION
signals concatenation not updated in module port connection
SHM dump run without access leads to SCHECK firing and Internal Exception
INTERR when $xm_mirror used in constructor of class
The simulation behavior different when added -linedebug option
Internal Exception error when force on unpacked array in GUI mode
problems with Tcl command value -keys
xmsim INTERRR while probing MESSAGE: probe_install_shm - switch
gq_taskfunc_prune_enable - incorrect type for VST_S_NONBLOCKING_ASSIGNMENT
XP_INSTANCE_INFO gives incorrect hierarchy for AOI
OSS profiler becomes unresponsive with xmsim for 12.5/12.6 version; improper exit in 12.4
E*, NOTPAR error causing many builds to fail
memory corruption during simulation with stack overflow, asan backtrace attached
Error due to permission differences between -process_save and -checkpoint_enable
E,NOTPAR happens at the xmelab with enable_var_opt_core
incorrect NOTPAR error on element of nested structs
xmelab INTERR: dt_get_known_datatype hit unknown datatype
Internal Error during profile dumping when using -enable_prof_info
GLS UPF simulation becomes unresponsive at _wordcopy_fwd_aligned via sslu_codprb_force()
initialization failure with -enable_var_opt_core
xmvlog: *E,UNSFRC (tb.sv,19
xmvlog_cg: *F,INTERR: INTERNAL EXCEPTION
xmelab Internal Exception when running with option -lwdgen
Symkeepsim stuck at popen call in prof_run_nm function
-enable_sync_comb not working in my environment
-enable_sensitivity_opt causing simulations to become unresponsive
Xprop LP simulation becomes unresponsive at time 0 with latest green release
Simulation fails without -access +rwc
xmelab: *F,INTERR: INTERNAL EXCEPTION
Questions about clocking block output delay
Improved messaging and reporting for XPUCI
INTERR: probe_install_shm - switch
xmelab internal error: tl_reg_prune_count - no pruned blocks
xmsim internal error with Cadence OCP VIP and enable_reg_update_inv option under newperf
INTERR: illegal list underflow
Incorrect or missing XFSTNC/XFSTND
simulation hang with performance options set
-access +r with xprop enabled causes misbehavior
Customer test case cu_optimize is taking 1243 seconds on nightly agile
csi-xmelab - CSI: *F,INTERR: INTERNAL EXCEPTION
Complex combinatorial assignment calculates the wrong value
Existing force on reg causes simulation internal error when specifying xmreplay
Wrong message from lmstat - Xcelium Multi Core - Simulation does not use Multi Core engine
INTERR: sv_seghandler in ssl_pwr_sn_driver with -lwdgen
SIGUSR message issues
Please add a note to this DPI warning telling the user how to fix it now
SIGSEGV from user DPI code must call ncdbg_fatal
Regarding ncvlog_cg: *E,UOPAW
ncvlog_cg: *E,UOPAW : Unsupported array assignment to output variable port
SIGRNG warning does not indicate what will happen
(SEAGATE) ncelab: *F,CGFAIL: Code generation failed for one or more modules.
SV unsupported syntax
SIGRNG warning does not explain the resulting behavior
elab warning to error
NOFDPI fatal error needs to include file/line where the DPI import exist
ncvlog_cg: *E,UOPAW Unsupported array assignment to output variable port 'oIqReqClear'.
xmsim: *E,OBNOVL: Object does not have a value: uvm_pkg::uvm_resource_db#(virtual interface bus_if)::m_show_msg.rsrc.
INTL_LKF: Xcelium giving unsupported feature issue
A switch that would print when the simulator entered or exited DPI calls
incorrect result due to wrong subtraction calculation
INT_LKFC: getting elab error SOLNAB Need support streaming concatenation to output/inout port of type unpacked struct
OOMR which has the vecotor index outside of declared range makes event triggered.
INT_LKFC:xmelab: *E,PCANLV:Expression connected to an 'output', 'inout', or 'ref' port/terminal must be an lvalue.
INT_LKFC:xmelab: *E,SOLVNT:Streaming concatenation expression of nets is not a legal lvalue
INT_LKFC:xmelab: *E,SOLVNT:Streaming concatenation expression of nets is not a legal lvalue
xmelab INTERR : cu_sigpv - unexpanded REG in concat
error: '_unit_0__t_fe_events_tlm_signal_list {aka struct <anonymous>}' has no member named '_a6'; did you mean '_a0'?
perf degradation for always block
ncvlog_cg: *E, UOPAW, Unsupported array assignment to output variable port
LP primary snapshot generation fails with - vst_declarative_items() - invalid class, class 1023
LP elaboration INTERR - cu_lpii_merge_ports_for_isolated_pot - !iso_pot
Clocking blocks deadcode - should support SV interface and SV checker
Support isolation on SV interface - with clocking blocks.
MESSAGE: vst_declarative_items() - invalid class
MESSAGE: sv_seghandler - trapno -1 addr(0xb)
ixcom:xmelab: *E,UNADIR: Unable to create directory
Elaboration error when running with "-dpiheader" and "-errorchk"
INTERNAL EXCEPTION xmelab during codegen
(Ehancement req.) foreach illegal for wildcard index of associative array(Currently unsupported)
significant performance issue using 3rd party VIP in xcelium
Default clocking appearing as a clocking block on profiler
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Cadence XCELIUM version 19.09.001

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