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version 15.20.001 | 9.3 Gb
Systems, Inc. , the leader in global electronic design innovation, has unveiled INCISIVE 15.20.001, the single-kernel verification platform for nanometer-scale designs that supports a unified verification methodology for the embedded software, control, data path, and analog/mixed-signal/RF design domains.
fixed in INCISIVE 15.20.001 1489447 DBG_ANALYZER idaDefineStyle() internal assertion when the same style is defined twice
idaDefineStyle() has character restrictions in style name which do not trigger an error
Problem in sending e events to waves with IDA
copy command error when using ida_database -open -name /tmp/aaa/ida.db command
IDA shows wrong stack when using "first of"
No syntax highlighting for file with .vh extension (file meant to be `included)
ESW_BETA: View of waveform window follow the DEBUG_LOCATION Marker.
Missing disassembly
Breaking in assembly window
[ESWD] Multi-image PC trace mode - No disassembly, No second assembler source
[ESWD] PC trace mode warning pop-up every time debug cores changed
ESW_BETA : breakpoints not saved when saving user state
Stars manager for ESWD shows name "EMPTY DATA" for all items
"Cores" window refresh issue
[ESWD] Callstack window doesn't work properly (showing redundant functions)
not able to use the "go to previous operation" of a core
Disassembly is not stepping into statically linked library function
multi-core issue in disassembly / source / WF
better granularity for PC / ASM code link
OS signal 11 when restoring User State
[ESWD] supporting step/back into dis-assembly window
missing disassembly with multi-elf processor trace mode
assignment via set_value() is not recorded using debug analyzer
output from filtered method is shown as emty (NULL structs and empty lists).
debug_analyzer script gives error message with garbage when using -file with the irun command
IDA: OPTNOML: Multiple -R option specified, only 1 required.
ida feature request - db filename in title bar of smartlog
Save user state dialogue box defaults to .sav
Monospace fond for disassembly code
when restoring the 'value' attribute after it was removed - the radix option disappears from the drop-down menu
debug analyzer gui does not comes up
Undocked source debugger window is fixed on top
issue when changing variableS radix
[ESWD] cannot change dis-assembly window to monospace font
Cannot change radix anymore after removing columns in time tables
[ESWD] Changing Radix on the Variables doesn't work
[ESWD] set monospace font as default of Source window
filtering issues of variables
[ESWD] Support showing Japanese charactoers on the Source Viewer
GUI freeze when changing Time table radix
Order tools are set in the Path impacts simulator behavior.
Unconsitent color map case sensitivity
'Jump Address' of Indago ESWD memory viewer doesn't work on testcase
'Lowest Address' and 'Highest Address' forms of the memory viewer tab are not wide enough
Support refinement for temporal evaluations
When recording from a particular time, ida does not record to smartlog.
Recording of $fwrite results in huge log
nested deep_copy not recorded
messages that contain *E that are not error messages are starred when i invoke the GUI (marked as error message
direct access arrow is shown on a specific line , but the blue scope indication is missing.
IDA - Warning/Error should be given when nothing is matching in the ignore_sv_files argument
Recording Issue: Flow information not recorded
IDA performance: -sv_flow option 40 times slower than without IDA
Performance: 10X Slowdown when running with both -log and -wave
Bad formatting of sprintf messages in smartlog
searcher doesn't show progress status
Add Smart print to log window focus
Support having direct access arrows from the smartLog when using VMM
Not able to filter message by destination file
Smartlog query not saving end time properly
Value of packed union is not displayed in the Variables window of IDA
IDA can not open arrays which are located under a struct in SV, as opposed to a class
wrong value shown in the variables table for automatic variable
variable table shows incorrect value while LOG shows correct value of local variable
watch window shows N/A values for local variables and function params in 14.20.017-s. this works fine in previous vers
OS Signal11 when clicking class in variable window
virtual interface values are not shown in the variables table when the vif is inside a class
bug in recording of a value of a function output
Be able to add array elements to time tables
Be able to see more levels of hierarchy in time tables
[ESWD] Encountered a parse error with R4 and M3
Add an API to specify an offset of the recorded TARMAC
ESWD crash when generating DB
Need descriptive error message for mismatched arch kind and tarmac file when creating esw db
[ESWD] Internal error when giving arch config file in pcshm flow
need a way to change disassembly_tool for ARM cores
Unclear error from Indago ESWD on architecture configuration file for generic processor trace format with single mode
ESWD not showing global variables
ESWD config disassembly_tool options issue
Regression failure fixes on avs151/tip_in
[ESWD] PC = FFFFFFFF in 32-bit mode
[ESWD] PC-trace mode 64-bit PC truncated into 32-bit in eswtrace.shm
Cannot trace a specific ESW function invocation, while the doc says it can
[ESWD] multiple warn/error of probe variable causes internal exception
[ESWD] [SOIO] Register probes installed using short name are not recorded under correct heirarchy in SHM
[ESWD] esw -probe -variable produces no output for pointer types int *, long * etc
Call stack shows "unknown function" from assembly source code
"Step over" & "run to method start/end" funtion from assembly source code does not work
Executed source lines are not shown as executed in source browser
Step over function does not work
Unclear error from Indago ESWD for user configuration file
case issue for db creation
multi-elf issue in processor trace mode
Indago GUI lost due to ESWD tool failure when getting call stack frames
not able to start indago
ESWD tool failure for DWARF functions with 0 address ranges
Internal Exception error when accessing global variables
Does register probe capture over 0x8000000 value?
[ESWD] probing register cause internal exception
SimCompare prematurely displays success though comparison is still running
SimVision incorrectly uses vpi_handle(vpiConstraintExpr, …) rather than vpi_iterate(vpiConstraintExpr, …)
Enable Simvision to query for rand_mode not only in randomization call
Users must be able to see rand_mode within the watch window at any time, not just within randomize calls
simvision fit data y-axis does not work
IDA seems to become unresponsive.
Simvision shows internal errors while retrieving class objects
checkbutton to filter LP objects in the Signal pane of the Design Browser
Is there a reason why uvm_subscriber aren't showing up in UVM-hier in Design browser?
IES becomes unresponsive when probing uvm hier.
"-nclibdirname" option in simvision dosn't work.
Unable to do Design File Search with 14.21.046 in customer's environment
SimVision Issue: Reinvoke vs Exit Setting
multiple progressdialog processes running
Simvision bring-up time is slower w/ 1801
simvision performance is poor when sim includes UPF
Database restore doesn't work for power domain information
simulation becomes unresposive when simvison is started with command script, but no probe command
missing connection in schematic tracer
Verilog processes are not sent to the waveform window from the schematic.
Sending certain VHDL record element to Schematic Window causes fatal error in ncsim
Please make showing the RTL symbols in the schematic viewer on by default
Simvision issues with Light weight debug snapshot fetaure
Trace drivers takes 10 minutes
driver tracing reports an expression as contributor but cannot trace further
Source browser does not work correctly for signal/instance which has Extended Identifier.
Moving in stack in Simvision takes a very long time
Source browser - design source files - filtering usability issues
Applying filters from the history does not work for "Design Files" tab of Source Browser
using $uvm:{} syntax for probing doesn't show source code in post processing
FSM viewer issue of VHDL design
Enhancement request: Turn off cursor movement while tracing.
Simvision timestamp (cursor) moves when double clicked in simvision
How to trace driver in the Source Browser without having the time marker change position
Simvision timestamp (cursor) moves when double clicked in simvision
SimVision to add an option that allows structs to display their first field in the waveform display
empty group does mess .svcf creation with missing trailing curly brace
Svwf is not loading in simvision
SimVision to add an option that allows Verilog fixed length strings to be automatically recognized as ASCII
trace driver in the Source Browser without changing the time cursor position
Simvision signal script saved incorrectly with empty groups
Unable to select signals using CTRL-A from signal selector area in wave window.
Default displayed radix of bit [31:0] in Source Browser should be hex
Assertion contributors are dublicated in waveform
IDA busy signal doesn't light up when expanding elements of the hierarchy
Large fault set gets the elaboration hang
… in fault_target does give a fatal error during elaboration
The elaboration with IFSS becomes unresponsive with netlist
elaboration run forever if fault instrumentation is enabled
NCELAB tool failure with gatelevel ifss simulation
Internal Exception when targeting SEU only during elaboration
IFR fails when snapshot does not have fault information
OS 11 on elaboration
glitches on good run simulation that are not on standard simulation
IFSS ncsim tool failure when using snapshot chekpoints and also having any dummy SystemC TB module being used.
Fault simulation memory usage increases after reset and rerun
"When others => null" state give warning [EMPSTM] even if all the state of cases are covered
halcheck: *E,NULLRG & halsynth: *E,EMTFNC comparing results with RC
halcheck: *F,HALSIG unable to proceed further due to a critical error
Support for NULLRG, NULSLC and NULLSTR halsynth error
Nodes fed into the flop reported as INF in HAL test coverage report
halcheck: *F,HALSIG: Unable to proceed further due to a critical error.
HAL "designinfo" broken when checked into design repository
hal stops with BLDSTP using -halsynth_nxg but not without
halsynth: *W,BBXSIG message – how to increase the limit
HAL - SLVUSE Violations - support for VHDL record types
Upgrade NEGIDX warning to error
HAL Enhacement: Accumulation of filters
HAL Rule IPRTEX and EXPIPC: need dummy tie off that isn't flagged by rule, ie ONE_TIE, ZERO_TIE
unexpected hal message SLVUSE with VHDL record type.
halcheck: *W,SLVUSE: Variable 'dacdatabsel' appearing in the sensitivity list is not used in the process block.
HAL warning SYNTXZ issued when OTHERS path does not exist
Linting enhancement: Support for SystemVerilog Case-Inside
halsynth: *F,CFESIG expExpr* getParamValueforUnpackedData(ss
halsynth: *E,SYSIGN : SystemVerilog 'case inside' construct is not supported
Error in supporting the local variable in property and sequence in IEV.
IFV DRM random crash on LSF
Tool failure in IEV using Reset Flow
illegal termination on formalverifier
REPERR at formalbuild step, not able to generate coverage, Tool run time becomes huge
Parallel persistent setting causing problem with Broadcom UNR
IEV tool failure during formalbuild
formal build INTERNAL EXCEPTION: xst_hasprotected on invalid VST type
IEV 14.20.013 UNR parallel_persistent_mode is no working
UNR execution with Primary and incremental sanpshot environment
IFV Connectivity : Assertions not generated on 14.20, while they are being properly generated on version 13.10.020
bb_gen problems with alias_module and tran switch
IFV SGE Distribution issue
Tool failure with IFV in LSF mode
IFV tool failure at formalbuild step
CFESIG in nc_mirror call when running formalbuild
IEV 14.1 Errors Out when Exiting the Tool in GUI Mode
compcnfg lib binding does not work with BIND2
compcnfg setting not working in BIND2 flow
Enhance reffile to use ENV variables in its path
ncelab: *F,INTERR: INTERNAL EXCEPTION
AMS could not handle "pwr" function in SPICE model
irun INTERR during parsing when module w/ `uselib is included twice w/ -amscompilefile
amsspice segmentation fault with error code 6
makelib compilation flow always requires a dummy file to be always present outside
Elab failure with cosim in spectre
support systemVerilog bind statements in AMS runs - when the bind statements are on SPICE blocks
elab tool failure in ius14.2s17 and beyond (works in ius14.1s11)
Files created by irun do not honor umask setting
VCD bus input don't reach digital blocks in AMS
irun versions after 14.20 do not show symbolic link but just fully resolved path
amsd control file no longer works for spice in EXT HDL in ADE L
Ncelab fails for SV assertions on Spice nets
Compcnfg view binding does not work with BIND2
Compcnfg option for view binding is not working
Add support fo rrelative paths and shell variable paths to amsd portmap reffile.
Allow reffile value to be specified via a UNIX env var
How to handle a cellview with multiple .v/.vams views in UNL?
Internal error in UNL testcase when switching to 15.10
UNL is erroring out on a cell totally unrelated to the actual problem in the design - fix elaboration error message
Incorrect current value reported by $cgav function
Incisive 14.2 and 15.1 doesn't queue for MMSIM tokens
AMS license queueing broken in INCISIVE 14.2 and 15.1
AMSD IEEE1801 enhanced test case for DoT flow
AMSD IEEE1801 Parametrizable power supply connect modules
AMS with CPF fails during elaboration
wreal simulations stops due to INPVINT/NINDEX0 errors
AMSD IEEE1801 Elaboration error LPACVF in case cds_implicit_tmpdir is used or when using ASSIGN TMP attribute
Incorrect conversion of UPF value when using the default predefined UPF_GNDZERO2SV_LOGIC table in UPF sims
the L2R_LPS on wreal array cause ncsim tool failure
AMSD IEEE1801 ncsim internal error with EAP build and extended ams test case
Remove VPI limitations in power smart IEs
AMSD IEEE1801 Include power supply connect modules in the IE CE report files generated by irun
cu_connected_through_port: the sizes for child and parent don't match (psize(10)
too many warnings during AMSLP simulations
ncelab becomes unresponsive on mixed-signal design with wreal models and CPF
The AMSLPS VPI function encountered an error
Omitting file name argument to +amsinfofile results in fatal error
ncelab tool failure when real variable connect to electrical port
SV interconnect array connected to different nettype fails
add the support of wreal of MSIE
Need incremental elab for design containing AMS
default discipline does not work on inh-conn
ncelab: *F,INTERR: INTERNAL EXCEPTION
ncelab fails to elaborate with inherited connections connect rules
ncelab internal error for chkdigdisp
NCSIM causes a tool failure on request for value from SimVision
ncelab Internal Exception when LP/CPF is used with SV and DMS
ncelab gives internal exception error with "ams_add_to_td_list - parent data already in child" message
ncelab tool failure because of ie card specification
enable wrealXState in VHDL for Mixed language Simulation
design gets Internal Error during ncelab 15.1 with amssie defaulted on
ncelab sv_seghandler - trapno -1 addr(0x20000024)
Adding a few irrelevant lines to an LP/DMS example prevents tool failure
Testcase fails with ihnConn_findSB - unresolved OOMR
ncelab Internal Exception with incisive version 14.20.009
NCELAB internal exception when using amsoptie
INTERNAL EXCEPTION in ncelab 15.10-s002
SV with nettypes and VHDL - crash
driver_update in conditional statement causes internal error
cannot issue an ida_probe command when the analog solver is present.
Simulation with warning WRMNZD when real has multiple drivers.
irun becomes unresponsive on compilation
$resolved_wudn_name needs further enhancement to give the top most (highest hierarchical level) name - always
E,NOTSUP occurs for task or function used in sv module
ncvlog internal error while initializing integer array in verilogams module
ncsim internal exception using -use_cm switch
Redundant WRMNZD warning for wreal
tran gate working incorrectly in wreal (DMS) simulations
irun ignores ie card in SV-UVM-AMSD flow when -run_coerce is on. Breaks multi-supply AMS verifications.
Modulus of a wreal produces an internal error
Question regarding "-nosort" for TCL assertion commands
Tool failure with -assertdebug
ncsim exits for MAX_ERROR when simvision causes UVMNCP error after an assertion
-assert_logging_error_off causes an RPTNAG error in 15.10.002 and newer
IUS14.2s004 fails by giving an assertion error during simulation
Simvision design search causes simulator Internal Exception
"-assert_logging_error_off" not changing the exit status to 0 for ncsim on assertion failure in 1420
IUS doesn't display ASRTST error after ncsc_assertion_on().
ncvlog_cg: *F,INTERR: INTERNAL EXCEPTION
long elaboration time with ncvlog_cg
always_comb hangs at time 0 with -linedebug or -access options.
ncsim becomes unresponsive in multiple always @* that references different bits of a signal
IUS simulation becomes unresonsive at 0ns.
internal exception when compiling UVM scoreboard : ncvlog_cg : gq_setwait - null/!SVHR VXLF_HEAP cached t_t
Ncvlog_cg failure in 14.22.012
ncsim goes into infinite loop by always@* in generate-for block
ncvlog_cg : Internal Exception Error while running a testcase
ability to handle longest static prefix of net array for always_comb/always_latch
Compilation Internal Exception 14.20.012 ( but works well with 12.20.30)
ncvlog_cg crashes with 15.10.00x
gc_addrelocation - offset out of bounds
*W,NLSPNA: longest static prefix for always_comb/always_latch is not supported for net array/struct
Warning NLSPNA longest static prefix for always_comb/always_latch
NLSPNA warning repeated for the same array
ncvlog_cg fatal error while executing tb generated from ET
ncvlog crash gc_addrelocation - offset field too large (2147483731d instructions)
Ncvlog crash gc_addrelocation - offset field too large (2147483731d instructions) after using -sparsearray switch
INTERNAL EXCEPTION: ncvlog_cg: gq_slfix - next sload not followed by a move
Ncvlog_cg fails in 14.20.014
ncvlog_cg: *F,INTERR: INTERNAL EXCEPTION MESSAGE: Unexpected signal #11
ncelab: *F,CGFAIL: Code generation failed for one or more modules.
testcase generates " gq_auto_swbwo - not found" crash
ncvlog_cg(64): Unexpected signal #11, program terminated (null)
[Mini regression] AVSFST14.22.014,015,016 Performance degradation with ATPG Parallel case
Customer got 'gc_addrelocation - offset field too large (2147483669d instructions)' crash
Running into internal gq_bopadd -d not tmp during code generation with 14.22.016
ncvlog_cg Internal Exception with internal error with code "gq_lhsvs - variable LHS ZDC"
INTERNAL EXCEPTION when elaboration using -nncbind flag on iBeta IUS15.10_v008
Request to invoke warning message when the flag 'ay' is used without 'alibext' flag
MSIE ncelab crash : tim_is_tch_dead - failed to find the provided tcheck
Compile error during parse spawned by elaboration bind
F,INTERR :gen_vst_expr - illegal KIND of expression
signal value does not propagate correctly to instance port.
ssue to bind a SV module on 2 snapshots using ncelab option -extbind
"irun -binding" does not work . However "ncelab -binding" works for 3-step flow.
ncvlog_cg fails on the attached testcase
NOTPAR msg seen when including lps_1801 during elab
INTERNAL EXCEPTION when using ER for 1524762
ncelab: *E,NOTPAR (./dut.sv,24 69): Illegal operand for constant expression [4(IEEE)].
part of vector slice is out of range and incisive returns the whole slice as 0
Implement a bbox flow to optimize IP reuse
ncelab CUMXVP Unsupported variable input port at mixed language boundary : VHDL array and unpacked array of typedef
[VHDL/SV] [Package Import] ncelab: *ECUMXVP Unsupported variable input port at mixed language boundary
Enhancment request to pass vhdl real to systemverilog
How to pass data between VHDL (record) and SystemVerilog (struct). TC attached, please review
array type imported with bounds defined by function gives cu_add_driver_to_vhdl_net_driver_list - net is boundary_net
Invalid assertion failure comparing sv bind port to vhdl signal via sv oomr with package import
array type imported with bounds defined by function call used in SVA gives "ast_integer_literal() - bad class"
Failure binding sv module to vhdl using ports defined via package import: MESSAGE: sv_seghandler - trapno -1 addr(0x3)
VHDL Package Import: Unable to connect SV enum port to VHDL enum using type imported from VHDL package
ncelab *E,TYCMPAT comparing sv port defined via vhdl package import to signal of same type in vhdl via OOMR
ncelab Internal Exception with nettmp_fetch - id out of range when binding SVA to VHDL
MAINVR - Support for mapping of verilog var unpacked array port to VHDL port
Mixed SV->VHDL OOMR Internal MESSAGE: gq_e_relational - RAWDATA/QP_CLASS
VHDL/SV ncelab INTERNAL ERROR: Unexpected data type mapping - finalize_sys_vlog_to_vhdl_data_type
Support connecting SV struct ports to VHDL record type ports through SV bind construct
SV with input port of certain types receive MAINVR error during ncelab when instantiated in VHDL
Mixed SV->VHDL Internal MESSAGE: dto_array_left - not array
ncelab INTERR: nettmp_fetch - id 34230294 is out of range
NC Internal Exception during elaboration
C compile failing during MSIE incremental elab
Single Run MSIE issue: Need support for event for OOPR
MSIE -nncbind : ncelab crash : vst_offset () - invalid class, class 513,
MSIE: genhref CPU Usage is not reported in irun.log file
ncelab TYCMPAT error in MSIE flow with multiple primary partitions
MSIE OOPR and -nncbind : Support for real port in OOPR
False port size mismatch warning (DSSSIZ)
MSIE -nncbind : testcase gives warning SVBNOI but does not give CUVHNF
ncelab error message sslu_descend - NULL ipp
MSIE : bind <bind_target_module>: <bind_target_instance_name> <bound_module_name> <bound_module_inst_name> not working
MSIE -nncbind : ncelab: *E,INCUSC [MSIE] : Module scope bind dot star port instantiation does not work
Need error for OOPR to unsupported object type/kind
*E DYNGHE hierarchical reference from primary to incr not allowed
mccodegen causes Internal Exception and unknown or ambiguous options ( -MSIESINGLEIRUN)
MSIE: Internal Error when elaborating the design hierarchy - incremental partition
MSIE : ncelab: *E,DSSUSC (./test.sv,14 35): [MSIE] Unsupported port connection identified.
During incremental, source files were re-compiled again, even they didn't change since primary build
ncelab error: code generation failed
MSIE OOPR : bit support needed for SOC Environment
ncelab error: sv_seghandler - trapno -1 addr((nil))
tranif gate turn-on/off delay is shown when data is changed only in the MSIE environment.
MSIE Simulation difference due to issues in OOPR extern file generation
two "-iprof" option will cause msie report false error
INTERR: gq_static_wormhole_offset - incompatible instance
A source code in primary snapshot is not updated in incremental elaboration
-primparallelelab -timedetail crash : irun: doit.c:14128: irun_td_mark: Assertion `irun_td_name == ((void *)0_`f failed
CU scope bind causes CUVHNF error
INTERNAL EXCEPTION: via_pib_field: No pot or pib assigning AOI to virtual interface array
Same module/package given on -top and -incrtop with -mkprimsnap should give an error
MSIE Internal Exception on DENALI VIP ENET Example
*E,DSSARR *E,DSSUFL: Please add support in MSIE for unsupported port type and array in port expression
IncElab: Incorrect behavior with tranif1 gate that crosses the snapshot boundary
1-irun MSIE : crash on incremental snapshot build
MSIE: ncelab Internal Exception sv_seghandler - trapno -1 addr(0xffffffffffffffff)
Please give warning that amkprimsnap -incrtop is deprecated name of -incrbind
INTERNAL EXCEPTION: vst_libname() - bad class, class 1023
Ncelab internal exception error while building incremental snapshot
SINGLE-MSIE: Incorrect DYNGPE error when OOMR goes from one ancillary top to another in same primary
NC crash during elaboration
ncelab error INCUSC : support for port of type struct on boundary port
STIDTP in 1-step irun MSIE flow with -primparamsok
ncelab *E,DSSUFL for arrays in port list
INTERR when trying to use MSIE
MSIE clone creation reaches endless loop
Incremental snapshot build takes more time even if the number of instances reduced
with 15.10.002, use tfile to disable tcheck doest work
ncelab: *E,DSSWLP (./dsswlp.sv,8 11): [MSIE] Too many module port connections.
vhdl instances not mapped to verilog primaries
Unexpected DIMERR on 1-step irun
ncvlog_cg crash with multi primary snapshot MSIE
Incremental elaboration gets INTERNAL EXCEPTION while running msie pii mode using single irun flow
MSIE unsupported connection type in 14.21.033 not in 14.21.023
Why does HREF generation take so long?
MSIE crash during elaborating primary partition
irun: *F,MLFNA error with MSIE flow
Need a release on 14.22 stream for reducing genhref time (irun with ano_ca_prune ) on GLS design
low CPU utilization during ncelab casued by accessing all source code
ncelab performance issue
low CPU utilization during ncelab casued by accessing all source code
ncelab performance improvement
Crash on FSL Treeruneer with latest 14.22 release
Elaboration time increased from 45 minutes to 15hrs
ncelab performance is slower in new netlist flow when compared to the existing netlist flow.
Request ability to specify more than 4 cores to -mcmaxcores
if_write() - closure - unable to locate dep src
[Mini regression GLS Elab Fail] MSG: if_write() - closure - unable to locate dep src /path_to/a_lib.v
MSIE : very long incremental elaboration step
CUVMPW when $clog2 participates in a typedef
logic type MDA causes ncelab internal cu_propagate_expand width conflict
code gives unexpected TYCMPAT error for a particular value of the parameter
INTERNAL EXCEPTION: sv_seghandler - trapno -1 addr(0xf) / cu_propagate_expand - width conflict
defparam argument caused elaboration Internall exception message cu_double_cmp_classspec
INTERNAL EXCEPTION: cu_build_glom_ots - VST_POT_LINK is NULL class 513
ncelab tool failure using UVM 1.2
SHIP-688 struct param overrides sometimes ignored
Internal error in GLV elaboration
$bits in interface is not working correctly
INTERNAL EXCEPTION: cu_build_glom_ots - VST_POT_LINK is not NULL, class 513
crash of simulator when loop over a two dimensional associative array indexed by class handle
Internal exception in elaboration.
irun fails with "vector ring corrupt" error
Internal error " rn_create_intoclassref " with virtual interface reference
ncelab failure on SV 'let' construct
unexpected ncelab: *E,TYCMPAT
Ncelab freezing at "Building instance overlay table"
ncelab internal error with just the production 14.10 releases
nc elab fails with *F,INTERR: INTERNAL EXCEPTION
Internal exception error during elaboration
ncelab tool Internal Exception
INTERNAL EXCEPTION: sv_seghandler - trapno -1 addr((nil)) with UVM CDNS-1.2
[NCELAB Internal Exception] request for zero bytes from ha_alloc()
ncelab: *F,INTERR: INTERNAL EXCEPTION (request for zero bytes from ha_alloc)
ncelab: *E,CUASMM: Invalid vector width (zero elements) specified for port 'STAT_S_AXI_GEN_RD_SEGMENTS' of
ncelab internal error: sv_seghandler - trapno -1 addr(0x4bd)
erroneous *E,TRASMM2 error
Problem propagating a parameter to a lower level module, $bits is used
ncelab INTERNAL EXCEPTION MESSAGE: vxt_valloc - unknown
`Ifdef not being honoured with `protected with multiple files
ncvlog: *F,NESTPT: illegal nested `protected source.
ncvlog SIGSEGV error when compiling verilog variant
ncelab: *F,INTERR : vst_metrics_sampled - vst_TY_tag - default
ncelab internal exception with message sv_seghandler - trapno
Comma causes ncvlog INTERNAL EXCEPTION
NCVLOG failure:: "p2_mpist - no table"
Freescale Ottawa AIOP_WRKS_FDMA NCVLOG *F, INTERR
Non-static class methods should not be allowed in constant expressions
Ncvlog internal error during CASE block compilation under uvm.
Simvision source browser shows bold line numbers (enable BPs) in wrong lines
INTERNAL EXCEPTION: ncvlog: p2_mpist - no table
enhance AMS to reflect high impedance from spice to "Z" on logic side
ncvlog internal error vst_datatype () - invalid class, class 850
ncvlog: *F,NESTPT: illegal nested `protected source. when compiling macro model
PORTNO error
ncvhdl_p internal error
elaboration error for port width mismatch
problems at VHDL/ SV boundary
ncsim extremely slow in forcing large unpacked array
Output of AND gate is 'x' when inputs are stable
LPS peformance bottleneck for huge array at corrution
ncsim internal error
Improved error reporting for ssslib errors in releasing objects in VPI
Internal error in ncsim while dumping SAIF file
IUS dumping SAIF without escape character
Internal Exception in $nc_deposit/$nc_release for empty string argument
assign statement value change 0–>x and x–>0 not well taken by tool at the start of simulation
"stream shell stream for power (method)" took 24% hits from one module in customer design
got into an infinite loop if it enables LPS in 14.20.008
Different IES version has different simaultion result when simulate DFT pattern
Need support for X->0/1 transition with dumpsaif
ncprotect Not encrypting all files and segmentation fault
ncsim: *F,INTERR: INTERNAL EXCEPTION sv_seghandler - trapno -1 addr((nil))
Null character on irun command causes uvm to issue fatal NOCOMP message
irun doesn't understand (i.e. ignore) +arg with "/*"
Irun always recompile all files even though nothing is changed
Testcase re-elaboration happens (without modifying any file) with option "-incdir".
ICFUC warning behavior is different between 14.1 and 14.21
irun: *E,CFNOPT error when writing logfile to null device
IDA fails at compilation with cryptic error message
irun keeps re-elaborating the design even if nothing has been changed
Recompile fails to detect changes with -ncerror
cannot open shared object by 14.1s33
use of irun nclibdirname option for specman e and hdl give error
"irun -helpsubject timing" does not show -maxdelay option
Error: dlopen failed: ./INCA_libs/irun.lnx8664.15.10.nc/specman.15.10.005-s/scratch/libsn_precomp.so
specman e + hdl snapshot load error for irun command having nclibdirpath
Irun doesn't recompile C source if -cpost option is used to compile DPI
specman e + hdl snapshot load error for irun command having nclibdirpath
irun fails to recompile after source change for elaboration error
ncelab: *E,CNTSEV: Error 'ICFUC' cannot increase severity promoting all warnings to errors
re-elaboration detected with no file change
irun: *E,CFNOPT error writing the log in a project directory
ncsim: *W,SMNPIE: "ida_probe …."
irun doesn't take nncbind as a hard elab option
MESSAGE: xprepare_license_or_die - maxIndex (-1) less than
VHDL/SV connecting enum ports gives - ncelab: *E,CFMPTC : VHDL port type is not compatible with Verilog.
Support for complete records, nested records and array of records in mixed OOMRs
ncelab: *E,DTYPMSM connecting array of enum ports using types defined by vhdl package import
VHDL to SV Port Binding: Need support for connecting array-of-enum ports
[NGTPMS] VHDL port (DCORE_SV_BIND.NR_STRUCT_I) type is not compatible with Verilog
$nc_mirror to vhdl where generic is referenced in signal declaration causes sv_fpehandler - user generated SIGFPE
LHS of SystemVerilog assignment is not toggling per RHS.
TRSRANGE error on VHDL port in SV testbench
Invalid *E,ASRTST comparing array of integer between VHDL and SV
VHDL record real is not propagated to Verilog struct real
SV OOMR to VHDL Package gives Internal at sim run time: sv_seghandler - trapno -1 addr(0x2c)
MSIE -nncbind : TCL Command "scope -show" results ncsim crash
MSIE got internal error with customer's PLI
design file search and design file list doesn't show files compiled in primary snapshot
simulation run time failure in via_inst_sanity_check
NY SOC 1-irun MSIE testcase simulation time degradation by 4X
Getting error when trying to use '-statement' switch in database command
mcdump on digital signal with AMS sims
Internal Exception error and stuck test when using mcdump with Indago recording
SCABRT: Signal SIGABRT raised outside of simulator
Please improve performance on mixed VHDL & Verilog with UVM SV testbench sims
Simvision does not show UVM hierarchy when a probe command is issued after hitting a breakpoint. in simulation.
Internal Exception due to ivia_pair_sanity_check
Simulation stuck with IDA recording
vst_name invalid class name when ida is dumped
SAIF dumping is taking too long.
SARC IDA Issue: Missing SmartLog Messages even though log recording enabled
ssl_shm_add_scope - not a scope
[NCSIM] internal error: map_xst_class_to_dwScopeType - kind? got:14
Internal exception occurred during simulation
simulation Internal Exception: vst_class
Failure with ncsim tool when recording with IDA
simulation crashed - sslu_shm_sv_update_queue - un-expected transaction type
TLM fifos / mailboxes can't be seen in Simvision waveform window
Unable to probe Mailbox
indago causes an ncsim tool failure
Saved command script doesn't preserve probe_unpacked_limit.
Show SystemVerilog mailbox transactions in simvision
probe command issued after build phase complete or at t=1 doesn't work on uvm hierarchy
INTERR when probing with "-depth all" in INCISIVE151. INCISIV142 works fine.
With -memdetail option the simulation run consumes 2x run time memory
nncbind with -iprof crash simulation
IES out of memory error with mem_iprof on design
ncsim failure wafter simulation finished when trying to write iprof database
Profiler does not show fork join inside a class method like how it is shown inside a module
-rdprofile gives PRFMXSO fatal error
IPROF failure in ncsim *F
iprof to better detail performance slowdown
Internal Exception while probing with -smart
$finish(2) does not execute final blocks in customer simulation
Wait statement is not unblocking after the extrusion is evaluated true
Failure caused by dumpsaif Tcl command used on SV RTL design
Possible memory leak in SV environment
ncvlog internal dt_is_array hit unknown datatype
nscim crash when refering to CB by hierarchical reference
Inconsistent force release semantics for wires and vairables
dynamic array in a task of class problem with fork join_none
Difference in Simulation Behavior with 14.22.016 compared to 14.22.008
Elab mem profile shows one checkpoint at 6.7 hours
Tool failure during simulation caused by uvm optimizations
ncsim : *F, INTERRR: INTERNAL EXCEPTION
IUS simulation Internal Exception in SoC environment
INTERNAL EXCEPTION: sv_fpehandler - SIGFPE not in_rts_xfer (1)
Failing PSL assertion in 14.20.009 was passing in 14.20.003
[Xprop] Reduce the pessimism in case statements
x-prop support for statement with timing delay
XPROP disabled for block with a struct member assignment
Performance degradation when enable xprop
Slow down of x5 when applying xprop
xfile support for hierarchical configuration using module name
Enabling Xprop causes 7x slowdown
xprop build time failure
XPROP not working on MDAs with ternary operator
Elaboration Internal Exception happens with x-prop enabled
Xprop is disabled for all always blocks if there is a generate block
xprop disabled for rtl blocks containing delay inside generate
Always_ff with synchronous reset is wrongly propagating X's
Xprop is wrongly generating 'x' as the output of a function with casez inside
xprop casez fails for 7 bits but works for 6 bits (both show enabled)
Reduce the pessimism in case statements
ncvlog_cg becomes unresponsive
Request support of env variables in xfile
xprop support for non-synthesizable delay statements
Request support of delays in non-blocking assignment for xprop sim
Xprop support for typedef datatypes as L-Value
Support using env variables in xfile and issue a warning if not supported
Xprop CASEZ/CASEX support for selects having x's in some bits positions
INVXPC: task or system task in block when void function call is used in procedural block.
Casez/Casex propagating 'X' with XPROP CAT mode enabled
xfile does not allow in-line comments
INTERNAL EXCEPTION: Unexcepted signal #11, program terminated (null) parsing xfile
Parser error for extra blank space
INTERNAL EXCEPTION parsing xfile
Support xprop for always with FF and latch (see attached testcase)
Have a warning when edge detection is disabled for always block
Simulation with xprop turned off at beginning of sim of snapshot elaborated with xprop is 29x that of snapshot without
always block doesnt work properly when XPROP is enabled
LP Sim - synchronous reset (always block) remains asserted even though clock and reset change
ncvlog_cg gq_taskfunc_prune_enable - incorrect type
Running with xprop shows a 3x performance hit
Xprop: ability to handle RTL assignment with delay
Unexpected Glitch in RTL Simulation in Xprop mode
Need an option to only show the places where x-prop was not applied
message in sufficient to debug problem "Unsupported LHS in assignment"
xprop changes behavior when data signal is used as a clock edge
False NBA and BA message on xp_elab.log
xrop option cause system failure with VHDL design in 15.1
X-prop : The result is different between 14.2/15.1 and 14.1.
xprop generating unexpected X
ncsim *F interr with coverage
sv_seghandler with multiple include_ccf
Using set_code_fine_grained_merging and set_refinement_resilience together
Internal error during coverage dumping
ucis_Open causes an internal error when invoked with long relative path
Expression coverage collecting runs very slow with generated statements
internal error rts_cov_nlevel_decomp_arith expr not found in the list
expression coverage issue : vector scoring.
set_com causing ncelab to take ~2 days to finish
Specifying -covdut becomes mandatory when using -lps_verify
coverage isn't shown for the RTL when -lps_verify flag is present
Conflict between -lps_verify and default coverage collection behavior
Coverage Model Creation takes a long time - using cross of more than 2 coverpoints and ignore_bins with
Coverage model dumping performance for large cross using with expression
Coverage Model Creation takes a long time
get_coverage not returning correct covered and total integers when used in UVM hierarchy
problem with functional transition coverage
Segfault : Error: 'analyze_vplan' command interrupted: failed to parse value for attribute 'buckets_filter'
Cross coverage duplicating bin entries when one of the covergroups has ignore bins in it
Running into internal gc_tmpmap - width mismtach during code generation with 14.22.008
IMC merge issue
INTERNAL EXCEPTION: cov_scope_get_modORgenName - unsupported class VST_D_BIND_SCOPE with nncbind
ncvlog crash with vst_identifier -bad class, class 581
Instance coverage not properly merging into type coverage results
NCSIM crash ::sv_seghandler - trapno -1 addr(0x100000a7d)
SVBUNSP: Coverage is not yet supported with this implementation
INTERNAL EXCEPTION during coverage dump (VST_D_BIND_SCOPE not supported)
late insertion of assertions & coverage modules
AVSFST 14.22.015 checkout incubation license for MSIE
lookup type from covergroup instance to covergroup type is broken
merge is failing for block level to chip level instance
crash during elaboration with debug build
wrong hierarchical names for per instance covergroup
Coverage dumping takes too long
coverage build performance is 3-4x slower than regular build
Very long simulation times when coverage is enabled
"xst_decomp_expr, unknown language 0" message while dumping coverage data at the end of simulation
toggle coverage support for array of struct
INCISIVE 14.10-s021: simulations fail with coverage
initreg0 cause 0->1 toggle coverage not collected
Overflow bits in assignment to wire confuse set_com in Toggle Coverage reporting
*F, INTERR Internal Exception in BCU testcases
SIGUSR with *W,SCV082 before that
W,SCV082: INTROSPECTION_INVALID_OPERATOR_0ARG - New with 14.1
E,SIGUSR 14.2 version: *W,SCV082: INTROSPECTION_INVALID_OPERATOR_0ARG
BOSCH: SCV: wrong scv_smart_ptr return type with SC_INCLUDE_FX defined
ncelab fatal error for GLS
Ncelab unexpected kind error during elaboration and fails to issue any failure information
ncelab: *F,INTERR: INTERNAL EXCEPTION when SDF is used
result of operator with bose sides having same constant with nagation is wrong
GLS, with SDF elab time Internal Exception
ncelab INTERNAL EXCEPTION: MESSAGE: gate_add_shadow_driver_info - not SHDWC
ncelab: *F,INTERR: INTERNAL EXCEPTION with INCISIVE 14.20-s006 and 14.20-s003
ncelab INTERNL EXCEPTION MESSAGE: ring id is -134217728 whereas max ring id is 134217727
Simulation result mismatches with probe enabled and probe disable in GLS zero delay mode
INTERNAL EXCEPTION: sv_seghandler - trapno -1 addr((nil)) in strap::get s …_if -cs
Gate Level Performance suffers slowdown with respect to RTL
sv_seghandler - trapno -1 addr((nil)) when $countdrivers is involved in RTL simulation
command line option for optimizing supply0 and supply1
Support for wildcard in "tcheck -off "
pathdelay_sense be a command-line argument for irun
large positive hold time is annotated if the hold time in SDF is negative value
ncelab Internal Exception with nettmp_replace - equivalent IDs (0) being requested annotating SDF
The path delay value is used for RETAIN annotation.
* (wildcard) should be applicable to ncsim tcheck tcl command
ncelab issues Internal Exception message for acg_verify_dest_tmp when multi SDF files being read
Simulation time SDF annotation to VITAL is not supported but can it be ignored?
The result of the timing check differs in ntc_level2 and ntc_level3.
[Mini regression failure] AVSFST14.22.011 failed with ths ATPG Serial FULLTIMING case
ncelab internal error when using -negdelay option
ncsim: *F,INTERR: INTERNAL EXCEPTION
NCSIM internal error :: sslu_get_sigp - scalar mismatch 2
ncsim fails on simport
seq_udp_delay not working when tfile used even though outside tfile instance parameters
Wrong timing violation is reported
Add the to wire through tcl script during simulation run time.
ncelab: *F,INTERR: INTERNAL EXCEPTION MESSAGE: Where is the sbo (sbo == NULL) in negdelay_adjust_intc_load()…
-negdelay causes ncelab: *F,INTERR: INTERNAL EXCEPTION when it used with 2 or more SDF files and -sdf_simtime
Elab tool failure because of uvm_config_db get in module
ncelab tool failure using a netlist created by UNL
simulation fails with sslu_get_sigp
Pulse which has the same width of gate delay dosn't pass the second gate of two casecaded one.
INTERNAL ERROR "MESSAGE: gc_orstore - unknown delay mode"
ncsim tool failure on LWD shm dumpping, without LWD ncsim in unresponsive
Powerdown replay issue with a function without inputs
ILLCNDM/SWFERR messages not helpful in indicating the source of problem
Add support for map_retention_cell
Gate-Level sim to support 1801 and instantiated isolation/retention cells
the tool should support for the PDF a Boolean expression composed of both

Download File Size:9.25 GB

Cadence INCISIVE version 15.20.001

€25

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