http://www.synplicity.com/products/synplifypremier


Synplicity Synplify Premier Design Planer v8.4


Synplify. Premier software builds up Synplicity's
industry-leading technology and adds new graph-based
physical synthesis for timing closure and simulator-like
visibility into operating FPGA devices for fast source-level
debugging.

Graph-Based Physical Synthesis
Invented by Synplicity, graph-based physical synthesis
improves timing closure by means of a single-pass physical
synthesis flow for 90nm FPGAs. Unlike ASICs, proximity does
not imply better timing in FPGAs. In graph-based physical
synthesis, pre-existing wires, switches, and placement sites
used for routing an FPGA can be represented as a detailed
routing resource graph. The notion of distance then changes
to a measure of delay and availability of wires. The
Synplify Premier solution's graph-based physical synthesis
technology merges optimization, placement, and routing to
generate a fully placed and physically optimized netlist,
providing rapid timing closure and a 5 - 20% timing
improvement.
Simulator-Like Visibility Into a Live FPGA
The Synplify Premier solution quickly finds functional
errors in FPGA designs by providing simulator-like
visibility into operating FPGA hardware. Based upon
technology from the Identify. product, the Synplify Premier
tool has integrated debugging software that allows designers
to annotate signals and conditions they want to monitor
directly in their RTL code. Once the FPGA has been
programmed, the RTL debugger is run, allowing users to view
actual signal values from a running FPGA directly in their
RTL code and debug it, in-system, and at the target
operating speed. Advanced triggering helps pinpoint design
problems

Download File Size:151.7 MB

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