Riviera-PRO is a high-performance verification platform
for ASIC and FPGA design teams, equipped with
mixed-language simulation engine and advanced debugging
tools. Riviera-PRO supports Electronic System Level (ESL)
Verification with SystemC and SystemVerilog, Assertions
Based Verification (ABV), Transaction Level Modeling (TLM)
and VHDL/Verilog Linting. Riviera-PRO works in command
line mode for maximum speed and is also equipped with a
powerful GUI for enhanced editing, tracing, and debugging.
Riviera-PRO is compatible with popular EDA products such
as Synopsys SmartModels, Novas, Denali, MATLAB and
Simulink.

Download File Size:142.16 MB

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