The Active-HDL suite is a comprehensive and totally integrated
environment for digital IC design and verification that employs
hardware description languages and C/C++ solutions. It provides
engineers and design teams with tools for efficient and vendor
independent design implementation and testing. The Active-HDL suite
has been designed based on customer suggestions and feedbacks to
ensure highest design productivity and remarkable ease-of-use.
Active-HDL supports even the most complex FPGA and ASIC designs by
providing the following key features:
.Design Entry
.Compiler
.High Performance Simulator
.Debugging
.Co-simulation
.Automated Testbench Generation
.Design Data Management
.FPGA Vendor Support
.Coverage and Profiler Metrics
.Documentation
.Legacy Design Support
.Actel Solutions
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