Riviera is a powerful, high performance ASIC and High
Density FPGA verification environment. Riviera is
optimized for long simulation runs and currently
supports the Unix, Linux and Windows NT/2000/XP
operating systems. The environment is modular and all
tools can be used as stand-alone applications or as
one integrated solution. The product includes:

VHDL / Verilog / Mixed simulation engine
Libraries and source files management system
Design Browser / Manager
HDL Editor
Advanced Debugging Tools
Assertion-based Verification
Waveform Viewer / Editor
Design Profiler / HDL Optimizer
Code Coverage
SystemC Support
Memory Viewer
Graphical User Interface (GUI)

http://www.aldec.com/Riviera/features.htm

Download File Size:55.48 MB

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